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    Memory arrays, ferroelectric transistors, and methods of reading and writing relative to memory cells of memory arrays
    1.
    发明授权
    Memory arrays, ferroelectric transistors, and methods of reading and writing relative to memory cells of memory arrays 有权

    公开(公告)号：US11276449B2

    公开(公告)日：2022-03-15

    申请号：US16838585

    申请日：2020-04-02

    申请人： Micron Technology, Inc.

    发明人： Durai Vishak Nirmal Ramaswamy ,  Wayne Kinney

    IPC分类号： G11C11/22 ,  H01L27/1159 ,  H01L21/28 ,  H01L29/78 ,  H01L27/11507 ,  H01L29/788

    摘要： Some embodiments include a ferroelectric transistor. The transistor has gate dielectric material configured as a first container, with the first container having a first inner surface. Metal-containing material is configured as a second container nested within said first container. The second container has a second inner surface with an area less than the first inner surface. Ferroelectric material is configured as a third container nested within the second container. The third container has a third inner surface with an area less than the second inner surface. Gate material is within the third container. Some embodiments include memory arrays having ferroelectric transistors as memory cells. Some embodiments include methods of writing/reading relative to memory cells of memory arrays when the memory cells are metal-ferroelectric-metal-insulator-semiconductor (MFMIS) transistors.

    Memory Arrays, Ferroelectric Transistors, and Methods of Reading and Writing Relative to Memory Cells of Memory Arrays
    2.
    发明申请
    Memory Arrays, Ferroelectric Transistors, and Methods of Reading and Writing Relative to Memory Cells of Memory Arrays 审中-公开

    公开(公告)号：US20200234751A1

    公开(公告)日：2020-07-23

    申请号：US16838585

    申请日：2020-04-02

    申请人： Micron Technology, Inc.

    发明人： Durai Vishak Nirmal Ramaswamy ,  Wayne Kinney

    IPC分类号： G11C11/22 ,  H01L21/28 ,  H01L27/1159 ,  H01L29/788 ,  H01L27/11507 ,  H01L29/78

    摘要： Some embodiments include a ferroelectric transistor. The transistor has gate dielectric material configured as a first container, with the first container having a first inner surface. Metal-containing material is configured as a second container nested within said first container. The second container has a second inner surface with an area less than the first inner surface. Ferroelectric material is configured as a third container nested within the second container. The third container has a third inner surface with an area less than the second inner surface. Gate material is within the third container. Some embodiments include memory arrays having ferroelectric transistors as memory cells. Some embodiments include methods of writing/reading relative to memory cells of memory arrays when the memory cells are metal-ferroelectric-metal-insulator-semiconductor (MFMIS) transistors.

    Memory Arrays, Ferroelectric Transistors, and Methods of Reading and Writing Relative to Memory Cells of Memory Arrays
    3.
    发明申请
    Memory Arrays, Ferroelectric Transistors, and Methods of Reading and Writing Relative to Memory Cells of Memory Arrays 审中-公开

    公开(公告)号：US20170309322A1

    公开(公告)日：2017-10-26

    申请号：US15134221

    申请日：2016-04-20

    申请人： Micron Technology, Inc.

    发明人： Durai Vishak Nirmal Ramaswamy ,  Wayne Kinney

    IPC分类号： G11C11/22 ,  H01L27/11507 ,  H01L29/788 ,  H01L29/78

    摘要： Some embodiments include a ferroelectric transistor. The transistor has gate dielectric material configured as a first container, with the first container having a first inner surface. Metal-containing material is configured as a second container nested within said first container. The second container has a second inner surface with an area less than the first inner surface. Ferroelectric material is configured as a third container nested within the second container. The third container has a third inner surface with an area less than the second inner surface. Gate material is within the third container. Some embodiments include memory arrays having ferroelectric transistors as memory cells. Some embodiments include methods of writing/reading relative to memory cells of memory arrays when the memory cells are metal-ferroelectric-metal-insulator-semiconductor (MFMIS) transistors.

    Memory Arrays, Ferroelectric Transistors, and Methods of Reading and Writing Relative to Memory Cells of Memory Arrays
    4.
    发明申请
    Memory Arrays, Ferroelectric Transistors, and Methods of Reading and Writing Relative to Memory Cells of Memory Arrays 有权

    公开(公告)号：US20220157364A1

    公开(公告)日：2022-05-19

    申请号：US17589603

    申请日：2022-01-31

    申请人： Micron Technology, Inc.

    发明人： Durai Vishak Nirmal Ramaswamy ,  Wayne Kinney

    IPC分类号： G11C11/22 ,  H01L27/1159 ,  H01L21/28 ,  H01L29/78 ,  H01L27/11507 ,  H01L29/788

    摘要： Some embodiments include a ferroelectric transistor. The transistor has gate dielectric material configured as a first container, with the first container having a first inner surface. Metal-containing material is configured as a second container nested within said first container. The second container has a second inner surface with an area less than the first inner surface. Ferroelectric material is configured as a third container nested within the second container. The third container has a third inner surface with an area less than the second inner surface. Gate material is within the third container. Some embodiments include memory arrays having ferroelectric transistors as memory cells. Some embodiments include methods of writing/reading relative to memory cells of memory arrays when the memory cells are metal-ferroelectric-metal-insulator-semiconductor (MFMIS) transistors.

    SELECTIVE READING OF MEMORY WITH IMPROVED ACCURACY
    9.
    发明申请
    SELECTIVE READING OF MEMORY WITH IMPROVED ACCURACY 有权
    具有提高精度的存储器的选择性读取

    公开(公告)号：US20150212871A1

    公开(公告)日：2015-07-30

    申请号：US14681471

    申请日：2015-04-08

    申请人： Micron Technology, Inc.

    发明人： Wayne Kinney ,  Gurtej S. Sandhu

    IPC分类号： G06F11/07 ,  G11C11/16

    CPC分类号： G06F11/0751 ,  G06F11/0727 ,  G11C11/16 ,  G11C11/1673 ,  G11C11/1677 ,  G11C29/021 ,  G11C2029/0411

    摘要： This disclosure relates to selectively performing a read with increased accuracy, such as a self-reference read, from a memory. In one aspect, data is read from memory cells, such as magnetoresistive random access memory (MRAM) cells, of a memory array. In response to detecting a condition associated with reading from the memory cells, a self-reference read can be performed from at least one of the memory cells. For instance, the condition can indicate that data read from the memory cells is uncorrectable via decoding of error correction codes (ECC). Selectively performing self-reference reads can reduce power consumption and/or latency associated with reading from the memory compared to always performing self-reference reads.

    摘要翻译： 本公开涉及从存储器中以增加的准确性（例如自引用读取）来选择性地执行读取。 在一个方面，从存储器阵列的诸如磁阻随机存取存储器（MRAM）单元的存储器单元读取数据。 响应于检测与从存储器单元的读取相关联的条件，可以从至少一个存储器单元执行自参考读取。 例如，条件可以指示通过纠错码（ECC）的解码，从存储器单元读取的数据是不可校正的。 与始终执行自参考读取相比，选择性执行自参考读取可以降低与从存储器读取相关联的功耗和/或延迟。

    Memory cell and an array of memory cells
    10.
    发明授权
    Memory cell and an array of memory cells 有权

    公开(公告)号：US11037942B2

    公开(公告)日：2021-06-15

    申请号：US16743088

    申请日：2020-01-15

    申请人： Micron Technology, Inc.

    发明人： Durai Vishak Nirmal Ramaswamy ,  Wayne Kinney ,  Marco Domenico Tiburzi

    IPC分类号： H01L27/115 ,  H01L27/11507 ,  H01L49/02 ,  H01L27/11514 ,  G11C11/21 ,  G11C11/24

    摘要： A memory cell includes a first electrode and a second electrode. A select device and a programmable device are in series with each other between the first and second electrodes. The select device is proximate and electrically coupled to the first electrode. The programmable device is proximate and electrically coupled to the second electrode. The programmable device includes a radially inner electrode having radially outer sidewalls. Ferroelectric material is radially outward of the outer sidewalls of the inner electrode. A radially outer electrode is radially outward of the ferroelectric material. One of the outer electrode or the inner electrode is electrically coupled to the select device. The other of the outer electrode and the inner electrode is electrically coupled to the second electrode. Arrays of memory cells are disclosed.