公开(公告)号：US20200051638A1

公开(公告)日：2020-02-13

申请号：US16518687

申请日：2019-07-22

Applicant: Micron Technology, Inc.

Inventor： Akira Goda ,  Haitao Liu ,  Changhyun Lee

IPC: G11C16/04 ,  G11C16/26 ,  G11C16/16 ,  G11C16/10 ,  H01L27/115 ,  H01L49/02 ,  G11C11/56 ,  G11C16/08 ,  G11C16/34 ,  H01L27/105

Abstract: Some embodiments include apparatuses and methods using first and second select gates coupled in series between a conductive line and a first memory cell string of a memory device, and third and fourth select gates coupled in series between the conductive line and a second memory cell string of the memory device. The memory device can include first, second, third, and fourth select lines to provide first, second, third, and fourth voltages, respectively, to the first, second, third, and fourth select gates, respectively, during an operation of the memory device. The first and second voltages can have a same value. The third and fourth voltages can have different values.

公开(公告)号：US10340286B2

公开(公告)日：2019-07-02

申请号：US16103669

申请日：2018-08-14

Applicant: Micron Technology, Inc.

Inventor： Akira Goda ,  Yushi Hu

IPC: H01L27/1157 ,  H01L27/11582 ,  H01L21/28

Abstract: Some embodiments include a NAND memory array which has a vertical stack of alternating insulative levels and wordline levels. The wordline levels have terminal ends corresponding to control gate regions. Charge-trapping material is along the control gate regions of the wordline levels, and is spaced form the control gate regions by charge-blocking material. The charge-trapping material along vertically adjacent wordline levels is spaced by intervening regions through which charge migration is impeded. Channel material extends vertically along the stack and is spaced from the charge-trapping material by charge-tunneling material. Some embodiments include methods of forming NAND memory arrays.

公开(公告)号：US20190198109A1

公开(公告)日：2019-06-27

申请号：US15850708

申请日：2017-12-21

Applicant: Micron Technology, Inc.

Inventor： Benben Li ,  Akira Goda ,  Ramey M. Abdelrahaman ,  Ian C. Laboriante ,  Krishna K. Parat

IPC: G11C16/04 ,  H01L27/11558 ,  H01L27/11524 ,  G11C8/08 ,  G11C11/408 ,  H01L27/24 ,  H01L27/11597 ,  H01L45/00

Abstract: Some embodiments include apparatuses and methods of forming such apparatuses. One of the apparatus includes first memory cells located in different levels in a first portion of the apparatus, second memory cells located in different levels in a second portion of the apparatus, a switch located in a third portion of the apparatus between the first and second portions, first and second control gates to access the first and second memory cells, an additional control gate located between the first and second control gates to control the switch, a first conductive structure having a thickness and extending perpendicular to the levels in the first portion of the apparatus, a first dielectric structure between the first conductive structure and charge-storage portions of the first memory cells, a second dielectric structure having a second thickness between the second conductive structure and a sidewall of the additional control gate, the second thickness being greater than the first thickness.

公开(公告)号：US20190088343A1

公开(公告)日：2019-03-21

申请号：US16186739

申请日：2018-11-12

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Carmine Miccoli ,  Christian Caillat ,  Akira Goda

IPC: G11C16/34 ,  G11C16/10 ,  G11C11/56 ,  G11C16/04

Abstract: Apparatus including an array of memory cells and a controller configured to program all memory cells of a grouping of memory cells that are to be respectively programmed to different levels other than a lowest level, corresponding to a lowest data state, to an intermediate level from the lowest level, and to respectively program all the memory cells of the grouping of memory cells that are to be respectively programmed to the different levels other than the lowest level to the different levels other than the lowest level from the intermediate level.

公开(公告)号：US10170189B2

公开(公告)日：2019-01-01

申请号：US15721007

申请日：2017-09-29

Applicant: Micron Technology, Inc.

Inventor： Akira Goda ,  Shafqat Ahmed ,  Khaled Hasnat ,  Krishna K. Parat

IPC: G11C16/04 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11582 ,  G11C16/26 ,  G11C16/34 ,  G11C16/12 ,  G11C16/14 ,  G11C16/06 ,  G11C16/10

Abstract: Apparatus and methods are disclosed, such as an apparatus that includes a string of charge storage devices associated with a pillar (e.g., of semiconductor material), a source gate device, and a source select device coupled between the source gate device and the string. Additional apparatus and methods are described.

公开(公告)号：US20180374860A1

公开(公告)日：2018-12-27

申请号：US16103669

申请日：2018-08-14

Applicant: Micron Technology, Inc.

Inventor： Akira Goda ,  Yushi Hu

IPC: H01L27/1157 ,  H01L21/8234 ,  H01L27/11582

CPC classification number: H01L27/11582 ,  H01L21/28282

Abstract: Some embodiments include a NAND memory array which has a vertical stack of alternating insulative levels and wordline levels. The wordline levels have terminal ends corresponding to control gate regions. Charge-trapping material is along the control gate regions of the wordline levels, and is spaced form the control gate regions by charge-blocking material. The charge-trapping material along vertically adjacent wordline levels is spaced by intervening regions through which charge migration is impeded. Channel material extends vertically along the stack and is spaced from the charge-trapping material by charge-tunneling material. Some embodiments include methods of forming NAND memory arrays.

公开(公告)号：US20180268909A1

公开(公告)日：2018-09-20

申请号：US15985973

申请日：2018-05-22

Applicant: Micron Technology, Inc.

Inventor： Akira Goda

IPC: G11C16/14 ,  G11C16/04 ,  H01L27/11556 ,  H01L27/11524 ,  G11C16/10

Abstract: Memory devices, memory cell strings and methods of operating memory devices are shown. Configurations described include directly coupling an elongated body region to a source line. Configurations and methods shown should provide a reliable bias to a body region for memory operations such as erasing.

公开(公告)号：US20180211714A1

公开(公告)日：2018-07-26

申请号：US15933498

申请日：2018-03-23

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Carmine Miccoli ,  Christian Caillat ,  Akira Goda

IPC: G11C16/34 ,  G11C11/56 ,  G11C16/04

CPC classification number: G11C16/3427 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3418 ,  G11C16/3459 ,  G11C2211/5622

Abstract: Apparatus including an array of memory cells and a controller configured to apply a particular programming pulse to a plurality of memory cells having a first subset of memory cells having respective desired data states that are lower than a particular data state and a second subset of memory cells having respective desired data states that are higher than or equal to the particular data state, to at least partially inhibit each memory cell of the first subset of memory cells from programming while not inhibiting any memory cell of the second subset of memory cells from programming and while applying the particular programming pulse, then to apply a subsequent programming pulse while not inhibiting any memory cell of the first subset of memory cells from programming other than any memory cell of the first subset of memory cells having its respective desired data state equal to a lowest data state, and while not inhibiting any memory cell of the second subset of memory cells from programming.

公开(公告)号：US09997247B2

公开(公告)日：2018-06-12

申请号：US15339374

申请日：2016-10-31

Applicant: Micron Technology, Inc.

Inventor： Akira Goda

IPC: G11C16/14 ,  H01L27/11524 ,  H01L27/11556 ,  G11C16/10 ,  G11C16/04

CPC classification number: G11C16/14 ,  G11C16/0483 ,  G11C16/10 ,  H01L27/11524 ,  H01L27/11556

Abstract: Memory devices, memory cell strings and methods of operating memory devices are shown. Configurations described include directly coupling an elongated body region to a source line. Configurations and methods shown should provide a reliable bias to a body region for memory operations such as erasing.

公开(公告)号：US20180122481A1

公开(公告)日：2018-05-03

申请号：US15721007

申请日：2017-09-29

Applicant: Micron Technology, Inc.

Inventor： Akira Goda ,  Shafqat Ahmed ,  Khaled Hasnat ,  Krishna K. Parat

IPC: G11C16/04 ,  G11C16/34 ,  G11C16/26 ,  G11C16/14 ,  G11C16/12 ,  G11C16/06 ,  G11C16/10

CPC classification number: G11C16/0483 ,  G11C16/0408 ,  G11C16/06 ,  G11C16/10 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3418 ,  G11C16/3427 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11582

Abstract: Apparatus and methods are disclosed, such as an apparatus that includes a string of charge storage devices associated with a pillar (e.g., of semiconductor material), a source gate device, and a source select device coupled between the source gate device and the string. Additional apparatus and methods are described.