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    Memory arrays comprising strings of memory cells and methods used in forming a memory array comprising strings of memory cells
    31.
    发明授权
    Memory arrays comprising strings of memory cells and methods used in forming a memory array comprising strings of memory cells 有权

    公开(公告)号：US12300318B2

    公开(公告)日：2025-05-13

    申请号：US17727515

    申请日：2022-04-22

    Applicant: Micron Technology, Inc.

    Inventor： Alyssa N. Scarbrough ,  Jordan D. Greenlee ,  John D. Hopkins

    IPC: H01L23/528 ,  G11C16/04 ,  H01L23/522 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27

    Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers directly above a conductor tier. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers. The channel-material strings directly electrically couple to conductor material of the conductor tier. Below the stack, an insulating tier is directly above the conductor tier and a metal-material tier is directly above the insulating tier. Conductive rings extend through the metal-material tier and the insulating tier to conductor material of the conductor tier. The conductive rings individually are around individual horizontal locations directly above which are individual of the channel-material strings. The channel-material strings directly electrically couple to the conductor material of the conductor tier through the insulating tier by the conductive rings. Other embodiments, including method, are disclosed.

    Memory arrays comprising strings of memory cells and methods used in forming a memory array comprising strings of memory cells
    34.
    发明授权
    Memory arrays comprising strings of memory cells and methods used in forming a memory array comprising strings of memory cells 有权

    公开(公告)号：US12176035B2

    公开(公告)日：2024-12-24

    申请号：US17583651

    申请日：2022-01-25

    Applicant: Micron Technology, Inc.

    Inventor： Alyssa N. Scarbrough ,  John D. Hopkins

    IPC: H01L29/76 ,  G11C16/04 ,  H01L23/522 ,  H01L23/528 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27

    Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers directly above a conductor tier. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers. The channel-material strings directly electrically couple with conductor material of the conductor tier. A through-array-via (TAV) region comprises TAVs that individually extend through the insulative tiers and the conductive tiers into the conductor tier. Individual of the TAVs comprises an upper portion directly above and joined with a lower portion. The individual TAVs in a vertical cross-section comprises at least one external upper jog surface. The individual TAVs comprise at least one external lower jog surface in the conductor tier in the vertical cross-section and that is below the upper jog surface. Other embodiments, including method, are disclosed.

    Memory Array Comprising Strings Of Memory Cells And Methods Including A Method Used In Forming A Memory Array Comprising Strings Of Memory Cells
    37.
    发明公开
    Memory Array Comprising Strings Of Memory Cells And Methods Including A Method Used In Forming A Memory Array Comprising Strings Of Memory Cells 审中-公开

    公开(公告)号：US20240203496A1

    公开(公告)日：2024-06-20

    申请号：US18588407

    申请日：2024-02-27

    Applicant: Micron Technology, Inc.

    Inventor： John D. Hopkins ,  Alyssa N. Scarbrough

    IPC: G11C16/04 ,  H01L21/28 ,  H01L29/423 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

    CPC classification number: G11C16/0483 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/42328 ,  H01L29/42344 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

    Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers comprising laterally-spaced memory-block regions having horizontally-elongated trenches there-between. Two of the first tiers have different vertical thicknesses relative one another. Channel-material strings of memory cells extend through the first tiers and the second tiers. Through the horizontally-elongated trenches, first conductive material is formed in void space in the two first tiers. The first conductive material fills the first tier of the two first tiers that has a smaller of the different vertical thicknesses in individual of the memory-block regions. The first conductive material less-than-fills the first tier of the two first tiers that has a larger of the different vertical thicknesses in the individual memory-block regions. Through the horizontally-elongated trenches, the first conductive material is isotropically etched from the first tier having the larger vertical thickness in the individual memory-block regions to leave the first conductive material in the first tier having the smaller vertical thickness in the individual memory-block regions. After the isotropically etching of the first conductive material and through the horizontally-elongated trenches, second conductive material is formed in the first tier having the larger vertical thickness in the individual memory-block regions. Other embodiments, including structure independent of method, are disclosed.

    Integrated Assemblies and Methods of Forming Integrated Assemblies
    38.
    发明公开
    Integrated Assemblies and Methods of Forming Integrated Assemblies 审中-公开

    公开(公告)号：US20240164093A1

    公开(公告)日：2024-05-16

    申请号：US18415928

    申请日：2024-01-18

    Applicant: Micron Technology, Inc.

    Inventor： Jordan D. Greenlee ,  Alyssa N. Scarbrough ,  John D. Hopkins

    IPC: H10B41/27 ,  G11C5/06 ,  H10B43/27

    CPC classification number: H10B41/27 ,  G11C5/06 ,  H10B43/27

    Abstract: Some embodiments include an integrated assembly having a memory region and another region adjacent the memory region. Channel-material-pillars are arranged within the memory region, and conductive posts are arranged within said other region. A source structure is coupled to lower regions of the channel-material-pillars. A panel extends across the memory region and said other region, and separates a first memory-block-region from a second memory-block-region. Doped-semiconductor-material is directly adjacent to the panel within the memory region and the other region. Rings laterally surround lower regions of the conductive posts. The rings are between the conductive posts and the doped-semiconductor-material. The rings include laminates of two or more materials, with at least one of said two or more materials being insulative. Some embodiments include methods for forming integrated assemblies.

    Memory Array Comprising Strings Of Memory Cells And Method Used In Forming A Memory Array Comprising Strings Of Memory Cells
    39.
    发明公开
    Memory Array Comprising Strings Of Memory Cells And Method Used In Forming A Memory Array Comprising Strings Of Memory Cells 审中-公开

    公开(公告)号：US20230276622A1

    公开(公告)日：2023-08-31

    申请号：US18144341

    申请日：2023-05-08

    Applicant: Micron Technology, Inc.

    Inventor： John D. Hopkins ,  Alyssa N. Scarbrough

    IPC: H10B41/27 ,  H10B41/10 ,  H10B43/10 ,  H10B43/27

    CPC classification number: H10B41/27 ,  H10B41/10 ,  H10B43/10 ,  H10B43/27

    Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers. The stack comprises laterally-spaced memory-block regions that have horizontally-elongated trenches there-between. Channel openings extend through the first tiers and the second tiers in the memory-block regions. Channel material of channel-material strings is formed in the channel openings and the channel material is formed in the horizontally-elongated trenches. The channel material is removed from the horizontally-elongated trenches and the channel material of the channel-material strings is left in the channel openings. After removing the channel material from the horizontally-elongated trenches, intervening material is formed in the horizontally-elongated trenches laterally-between and longitudinally-along immediately-laterally-adjacent of the memory-block regions. Other embodiments, including structure independent of method, are disclosed.

    Memory array comprising strings of memory cells and method used in forming a memory array comprising strings of memory cells
    40.
    发明授权
    Memory array comprising strings of memory cells and method used in forming a memory array comprising strings of memory cells 有权

    公开(公告)号：US11683932B2

    公开(公告)日：2023-06-20

    申请号：US17006634

    申请日：2020-08-28

    Applicant: Micron Technology, Inc.

    Inventor： John D. Hopkins ,  Alyssa N. Scarbrough

    IPC: H01L27/11582 ,  H10B41/27 ,  H10B41/10 ,  H10B43/10 ,  H10B43/27

    CPC classification number: H10B41/27 ,  H10B41/10 ,  H10B43/10 ,  H10B43/27

    Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers. The stack comprises laterally-spaced memory-block regions that have horizontally-elongated trenches there-between. Channel openings extend through the first tiers and the second tiers in the memory-block regions. Channel material of channel-material strings is formed in the channel openings and the channel material is formed in the horizontally-elongated trenches. The channel material is removed from the horizontally-elongated trenches and the channel material of the channel-material strings is left in the channel openings. After removing the channel material from the horizontally-elongated trenches, intervening material is formed in the horizontally-elongated trenches laterally-between and longitudinally-along immediately-laterally-adjacent of the memory-block regions. Other embodiments, including structure independent of method, are disclosed.

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