公开(公告)号：US10608012B2

公开(公告)日：2020-03-31

申请号：US16111357

申请日：2018-08-24

Applicant: Micron Technology, Inc.

Inventor： Guangyu Huang ,  Haitao Liu ,  Chandra V. Mouli ,  Srinivas Pulugurtha

IPC: H01L27/11582 ,  H01L21/02 ,  H01L29/16 ,  H01L29/20 ,  H01L29/24 ,  H01L29/04 ,  H01L29/165 ,  H01L29/66 ,  H01L29/22 ,  H01L21/28

Abstract: Memory devices and electronic systems include an array of vertical memory cells positioned along respective vertical channels to define vertical memory strings. Each of the vertical channels includes a channel material exhibiting an electron mobility of at least about 30 cm2/(V·s) and a room temperature band gap of at least about 1.40 eV (e.g., zinc oxide, silicon carbide, indium phosphide, indium gallium zinc oxide, gallium arsenide, or molybdenum disulfide) and a bottom plug material exhibiting a room temperature band gap of less than about 1.10 eV (e.g., silicon germanium, germanium, or indium gallium arsenide). Methods of fabricating a memory device include forming such a bottom plug material within vertical channels and forming such a channel material electrically coupled to the bottom plug material.

公开(公告)号：US11937423B2

公开(公告)日：2024-03-19

申请号：US17746649

申请日：2022-05-17

Applicant: Micron Technology, Inc.

Inventor： Luan C. Tran ,  Guangyu Huang ,  Haitao Liu

IPC: H10B41/27 ,  G11C5/06 ,  H10B41/35 ,  H10B41/60 ,  H10B43/27 ,  H10B43/35

CPC classification number: H10B41/27 ,  G11C5/063 ,  H10B41/35 ,  H10B41/60 ,  H10B43/27 ,  H10B43/35

Abstract: A method used in forming a memory array, comprises forming a substrate comprising a conductive tier, an insulator etch-stop tier above the conductive tier, a select gate tier above the insulator etch-stop tier, and a stack comprising vertically-alternating insulative tiers and wordline tiers above the select gate tier. Etching is conducted through the insulative tiers, the wordline tiers, and the select gate tier to and stopping on the insulator etch-stop tier to form channel openings that have individual bottoms comprising the insulator etch-stop tier. The insulator etch-stop tier is penetrated through to extend individual of the channel openings there-through to the conductive tier. Channel material is formed in the individual channel openings elevationally along the insulative tiers, the wordline tiers, and the select gate tier and is directly electrically coupled with the conductive material in the conductive tier. Structure independent of method is disclosed.

公开(公告)号：US20230171962A1

公开(公告)日：2023-06-01

申请号：US18096341

申请日：2023-01-12

Applicant: Micron Technology, Inc.

Inventor： Guangyu Huang ,  Haitao Liu ,  Chandra Mouli ,  Justin B. Dorhout ,  Sanh D. Tang ,  Akira Goda

IPC: H10B43/27 ,  H01L23/522 ,  H10B43/35

CPC classification number: H10B43/27 ,  H01L23/5226 ,  H01L28/00 ,  H10B43/35

Abstract: Some embodiments include an integrated structure having vertically-stacked conductive levels. Upper conductive levels are memory cell levels, and a lower conductive level is a select device level. Conductively-doped semiconductor material is under the select device level. Channel material extends along the memory cell levels and the select device level, and extends into the conductively-doped semiconductor material. A region of the channel material that extends into the conductively-doped semiconductor material is a lower region of the channel material and has a vertical sidewall. Tunneling material, charge-storage material and charge-blocking material extend along the channel material and are between the channel material and the conductive levels. The tunneling material, charge-storage material and charge-blocking material are not along at least a portion of the vertical sidewall of the lower region of the channel material, and the conductively-doped semiconductor material is directly against such portion. Some embodiments include methods of forming integrated structures.

公开(公告)号：US11569266B2

公开(公告)日：2023-01-31

申请号：US17308766

申请日：2021-05-05

Applicant: Micron Technology, Inc.

Inventor： Guangyu Huang ,  Haitao Liu ,  Chandra Mouli ,  Justin B. Dorhout ,  Sanh D. Tang ,  Akira Goda

IPC: H01L27/11582 ,  H01L23/522 ,  H01L27/1157 ,  H01L49/02

Abstract: Some embodiments include an integrated structure having vertically-stacked conductive levels. Upper conductive levels are memory cell levels, and a lower conductive level is a select device level. Conductively-doped semiconductor material is under the select device level. Channel material extends along the memory cell levels and the select device level, and extends into the conductively-doped semiconductor material. A region of the channel material that extends into the conductively-doped semiconductor material is a lower region of the channel material and has a vertical sidewall. Tunneling material, charge-storage material and charge-blocking material extend along the channel material and are between the channel material and the conductive levels. The tunneling material, charge-storage material and charge-blocking material are not along at least a portion of the vertical sidewall of the lower region of the channel material, and the conductively-doped semiconductor material is directly against such portion. Some embodiments include methods of forming integrated structures.

公开(公告)号：US20210375925A1

公开(公告)日：2021-12-02

申请号：US17445157

申请日：2021-08-16

Applicant: Micron Technology, Inc.

Inventor： Guangyu Huang ,  Haitao Liu ,  Chandra V. Mouli ,  Srinivas Pulugurtha

IPC: H01L27/11582 ,  H01L21/02 ,  H01L29/16 ,  H01L29/20 ,  H01L29/24 ,  H01L29/04 ,  H01L29/165 ,  H01L29/66 ,  H01L29/22 ,  H01L21/28

Abstract: Memory devices and electronic systems include an array of vertical memory cells positioned along respective vertical channels to define vertical memory strings. Each of the vertical channels includes a channel material exhibiting an electron mobility of at least about 30 cm2/(V·s) and a room temperature band gap of at least about 1.40 eV (e.g., zinc oxide, silicon carbide, indium phosphide, indium gallium zinc oxide, gallium arsenide, or molybdenum disulfide) and a bottom plug material exhibiting a room temperature band gap of less than about 1.10 eV (e.g., silicon germanium, germanium, or indium gallium arsenide). Methods of fabricating a memory device include forming such a bottom plug material within vertical channels and forming such a channel material electrically coupled to the bottom plug material.

公开(公告)号：US11024643B2

公开(公告)日：2021-06-01

申请号：US16541029

申请日：2019-08-14

Applicant: Micron Technology, Inc.

Inventor： Guangyu Huang ,  Haitao Liu ,  Chandra Mouli ,  Justin B. Dorhout ,  Sanh D. Tang ,  Akira Goda

IPC: H01L27/11582 ,  H01L23/522 ,  H01L27/1157 ,  H01L49/02

Abstract: Some embodiments include an integrated structure having vertically-stacked conductive levels. Upper conductive levels are memory cell levels, and a lower conductive level is a select device level. Conductively-doped semiconductor material is under the select device level. Channel material extends along the memory cell levels and the select device level, and extends into the conductively-doped semiconductor material. A region of the channel material that extends into the conductively-doped semiconductor material is a lower region of the channel material and has a vertical sidewall. Tunneling material, charge-storage material and charge-blocking material extend along the channel material and are between the channel material and the conductive levels. The tunneling material, charge-storage material and charge-blocking material are not along at least a portion of the vertical sidewall of the lower region of the channel material, and the conductively-doped semiconductor material is directly against such portion. Some embodiments include methods of forming integrated structures.

公开(公告)号：US10892268B2

公开(公告)日：2021-01-12

申请号：US16421262

申请日：2019-05-23

Applicant: Micron Technology, Inc.

Inventor： Haitao Liu ,  Chandra Mouli ,  Sergei Koveshnikov ,  Dimitrios Pavlopoulos ,  Guangyu Huang

IPC: H01L21/28 ,  H01L27/11556 ,  H01L27/11582

Abstract: Some embodiments include an integrated structure having a stack of alternating dielectric levels and conductive levels, and having vertically-stacked memory cells within the conductive levels. An opening extends through the stack. Channel material is within the opening and along the memory cells. At least some of the channel material contains germanium.

公开(公告)号：US20210005626A1

公开(公告)日：2021-01-07

申请号：US16983664

申请日：2020-08-03

Applicant: Micron Technology, Inc.

Inventor： Akira Goda ,  Haitao Liu ,  Jin Chen ,  Guangyu Huang ,  Mojtaba Asadirad

IPC: H01L27/11573 ,  G11C16/08 ,  G11C16/24 ,  H01L21/02 ,  H01L23/528 ,  H01L23/532 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/04 ,  H01L29/16 ,  H01L29/36 ,  H01L29/66 ,  H01L29/78 ,  G11C16/04

Abstract: Some embodiments include apparatuses, and methods of forming the apparatuses. Some of the apparatuses include a first group of conductive materials interleaved with a first group of dielectric materials, a pillar extending through the conductive materials and the dielectric materials, memory cells located along the first pillar, a conductive contact coupled to a conductive material of the first group of conductive materials, and additional pillars extending through a second group of conductive materials and a second group of dielectric materials. The second pillar includes a first portion coupled to a conductive region, a second portion, a third portion, and a fourth portion coupled to the conductive contact. The second portion is located between the first and third portions. The second portion of each of the additional pillars is part of a piece of material extending from a first pillar to a second pillar of the additional pillars.

公开(公告)号：US10418379B2

公开(公告)日：2019-09-17

申请号：US15945215

申请日：2018-04-04

Applicant: Micron Technology, Inc.

Inventor： Guangyu Huang ,  Haitao Liu ,  Chandra Mouli ,  Justin B. Dorhout ,  Sanh D. Tang ,  Akira Goda

IPC: H01L27/11582 ,  H01L23/522 ,  H01L27/1157 ,  H01L49/02

Abstract: Some embodiments include an integrated structure having vertically-stacked conductive levels. Upper conductive levels are memory cell levels, and a lower conductive level is a select device level. Conductively-doped semiconductor material is under the select device level. Channel material extends along the memory cell levels and the select device level, and extends into the conductively-doped semiconductor material. A region of the channel material that extends into the conductively-doped semiconductor material is a lower region of the channel material and has a vertical sidewall. Tunneling material, charge-storage material and charge-blocking material extend along the channel material and are between the channel material and the conductive levels. The tunneling material, charge-storage material and charge-blocking material are not along at least a portion of the vertical sidewall of the lower region of the channel material, and the conductively-doped semiconductor material is directly against such portion. Some embodiments include methods of forming integrated structures.

公开(公告)号：US10381365B2

公开(公告)日：2019-08-13

申请号：US15677914

申请日：2017-08-15

Applicant: Micron Technology, Inc.

Inventor： Haitao Liu ,  Chandra Mouli ,  Sergei Koveshnikov ,  Dimitrios Pavlopoulos ,  Guangyu Huang

IPC: H01L27/115 ,  H01L27/11556 ,  H01L21/28 ,  H01L27/11582

Abstract: Some embodiments include an integrated structure having a stack of alternating dielectric levels and conductive levels, and having vertically-stacked memory cells within the conductive levels. An opening extends through the stack. Channel material is within the opening and along the memory cells. At least some of the channel material contains germanium.