公开(公告)号：US20220352383A1

公开(公告)日：2022-11-03

申请号：US17864244

申请日：2022-07-13

Applicant: Micron Technology, Inc.

Inventor： Srinivas Pulugurtha ,  Litao Yang ,  Haitao Liu ,  Kamal M. Karda

IPC: H01L29/786 ,  H01L27/11514 ,  H01L29/49 ,  H01L27/108 ,  H01L29/51

Abstract: Some embodiments include integrated memory. The integrated memory includes a first series of first conductive structures and a second series of conductive structures. The first conductive structures extend along a first direction. The second conductive structures extend along a second direction which crosses the first direction. Pillars of semiconductor material extend upwardly from the first conductive structures. Each of the pillars includes a lower source/drain region, an upper source/drain region, and a channel region between the lower and upper source/drain regions. The lower source/drain regions are coupled with the first conductive structures. Insulative material is adjacent sidewall surfaces of the pillars. The insulative material includes ZrOx, where x is a number greater than 0. The second conductive structures include gating regions which are spaced from the channel regions by at least the insulative material. Storage elements are coupled with the upper source/drain regions.

公开(公告)号：US11462544B2

公开(公告)日：2022-10-04

申请号：US16161381

申请日：2018-10-16

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  Kamal M. Karda ,  Wolfgang Mueller ,  Sourabh Dhir ,  Robert Kerr ,  Sangmin Hwang ,  Haitao Liu

IPC: H01L27/108 ,  H01L21/762 ,  H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L29/423 ,  H01L29/08 ,  H01L23/528

Abstract: An array of recessed access gate lines includes active area regions having dielectric trench isolation material there-between. The trench isolation material comprises dielectric projections extending into opposing ends of individual active area regions under an elevationally outermost surface of material of the active area regions. The active area material is elevationally over the dielectric projections. Recessed access gate lines individually extend transversally across the active area regions and extend between the ends of immediately end-to-end adjacent active area regions within the dielectric trench isolation material. Other arrays are disclosed, as are methods.

公开(公告)号：US11411118B2

公开(公告)日：2022-08-09

申请号：US17017426

申请日：2020-09-10

Applicant: Micron Technology, Inc.

Inventor： Srinivas Pulugurtha ,  Litao Yang ,  Haitao Liu ,  Kamal M. Karda

IPC: H01L29/786 ,  H01L27/11514 ,  H01L29/49 ,  H01L27/108 ,  H01L29/51

Abstract: Some embodiments include integrated memory. The integrated memory includes a first series of first conductive structures and a second series of conductive structures. The first conductive structures extend along a first direction. The second conductive structures extend along a second direction which crosses the first direction. Pillars of semiconductor material extend upwardly from the first conductive structures. Each of the pillars includes a lower source/drain region, an upper source/drain region, and a channel region between the lower and upper source/drain regions. The lower source/drain regions are coupled with the first conductive structures. Insulative material is adjacent sidewall surfaces of the pillars. The insulative material includes ZrOx, where x is a number greater than 0. The second conductive structures include gating regions which are spaced from the channel regions by at least the insulative material. Storage elements are coupled with the upper source/drain regions.

公开(公告)号：US20220208256A1

公开(公告)日：2022-06-30

申请号：US17545756

申请日：2021-12-08

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Haitao Liu ,  Karthik Sarpatwari ,  Durai Vishak Nirmal Ramaswamy

IPC: G11C11/4097 ,  G11C11/4096 ,  H01L27/108 ,  G11C11/4094

Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes multiple levels of two-transistor (2T) memory cells vertically arranged above a substrate. Each 2T memory cell includes a charge storage transistor having a gate, a write transistor having a gate, a vertically extending access line, and a single bit line pair. The source or drain region of the write transistor is directly coupled to a charge storage structure of the charge storage transistor. The vertically extending access line is coupled to gates of both the charge storage transistor and the write transistor of 2T memory cells in multiple respective levels of the multiple vertically arranged levels. The vertically extending access line and the single bit line pair are used for both write operations and read operations of each of the 2T memory cells to which they are coupled.

公开(公告)号：US20220181341A1

公开(公告)日：2022-06-09

申请号：US17110439

申请日：2020-12-03

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Haitao Liu ,  Michael Violette ,  Mark A. Helm ,  Guangyu Huang ,  Vladimir Mikhalev

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L29/417 ,  H01L29/78 ,  H01L27/088 ,  G11C16/04

Abstract: Apparatus having a transistor connected between a voltage node and a load node, where the transistor includes a dielectric material overlying a semiconductor material including fins and having a first conductivity type, a conductor overlying the dielectric material, first and second extension region bases formed in the semiconductor material and having a second conductivity type, first and second extension region risers formed overlying respective first and second extension region bases and having the second conductivity type, and first and second source/drain regions formed in respective first and second extension region risers and having the second conductivity type at greater conductivity levels than their respective extension region risers, as well as method of forming similar transistors.

公开(公告)号：US20220181254A1

公开(公告)日：2022-06-09

申请号：US17681377

申请日：2022-02-25

Applicant: Micron Technology, Inc.

Inventor： Naveen Kaushik ,  Yoshihiko Kamata ,  Richard J. Hill ,  Kyle A. Ritter ,  Tomoko Ogura Iwasaki ,  Haitao Liu

IPC: H01L23/522 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11556

Abstract: Some embodiments include an assembly having channel-material-structures, and having memory cells along the channel-material-structures. The memory cells include charge-storage-material. Linear-conductive-structures are vertically offset from the channel-material-structures and are electrically coupled with the channel-material-structures. Intervening regions are between the linear-conductive-structures. Conductive-shield-structures are within the intervening regions. The conductive-shield-structures are electrically coupled with a reference-voltage-source.

公开(公告)号：US20220149046A1

公开(公告)日：2022-05-12

申请号：US17093869

申请日：2020-11-10

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Haitao Liu ,  Litao Yang

IPC: H01L27/108 ,  G11C11/408

Abstract: Systems, methods and apparatus are provided for an array of vertically stacked memory cells having vertically oriented access devices having a first source/drain region and a second source drain region vertically separated by a channel region, and gates opposing the channel region, vertically oriented access lines coupled to the gates and separated from a channel region by a gate dielectric. The memory cells have horizontally oriented storage nodes coupled to the first source/drain region and horizontally oriented digit lines coupled to the second source/drain regions.

公开(公告)号：US20220109000A1

公开(公告)日：2022-04-07

申请号：US17062222

申请日：2020-10-02

Applicant: Micron Technology, Inc.

Inventor： Haitao Liu ,  Kunal R. Parekh

IPC: H01L27/11582 ,  H01L29/47 ,  H01L21/285 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11573

Abstract: A microelectronic device comprises a stack structure, cell pillar structures, an active body structure, digit line structures, and control logic devices. The stack structure comprises vertically neighboring tiers, each of the vertically neighboring tiers comprising a conductive structure and an insulative structure vertically neighboring the conductive structure. The cell pillar structures vertically extend through the stack structure and each comprise a channel material and an outer material stack horizontally interposed between the channel material and the stack structure. The active body structure vertically overlies the stack structure and is in contact with the channel material of the cell pillar structures. The active body structure comprises a metal material having a work function greater than or equal to about 4.7 electronvolts. The digit line structures vertically underlie the stack structure and are coupled to the cell pillar structures. Memory devices, electronic systems, and methods of forming a microelectronic device are also described.

公开(公告)号：US20220068929A1

公开(公告)日：2022-03-03

申请号：US17007327

申请日：2020-08-31

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Deepak Chandra Pandey ,  Litao Yang ,  Srinivas Pulugurtha ,  Yunfei Gao ,  Haitao Liu

IPC: H01L27/108 ,  H01L49/02 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L29/66

Abstract: Systems, methods and apparatus are provided for an array of vertically stacked memory cells having horizontally oriented access devices having a first source/drain region and a second source drain region separated by a channel region, and gates opposing the channel region, vertically oriented access lines coupled to the gates and separated from a channel region by a gate dielectric. The memory cells have horizontally oriented storage nodes coupled to the second source/drain region and horizontally oriented digit lines coupled to the first source/drain regions. In one example, an insulator material is formed on a surface of the first source/drain region and a conductor material formed on the insulator material to form a metal insulator semiconductor (MIS) interface between the horizontally oriented digit lines and the first source/drain regions of the horizontally oriented access devices.

公开(公告)号：US20220068927A1

公开(公告)日：2022-03-03

申请号：US17004917

申请日：2020-08-27

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Haitao Liu

IPC: H01L27/108 ,  G11C8/14

Abstract: Systems, methods and apparatus are provided for depositing alternating layers of dielectric material and sacrificial material in repeating iterations to form a vertical stack, forming a plurality of vertical openings through the vertical stack to form elongated vertical, pillar columns with sidewalls in the vertical stack, patterning the pillar columns to expose a location to form a channel region, selectively removing a portion of the sacrificial material to form first horizontal openings in the first horizontal direction in the sidewalls of the elongated vertical, pillar columns, and depositing a channel material in the first horizontal openings to form the channel region within the sidewalls for the horizontally oriented access devices.