公开(公告)号：US20230052468A1

公开(公告)日：2023-02-16

申请号：US17399283

申请日：2021-08-11

Applicant: Micron Technology, Inc.

Inventor： M. Jared Barclay ,  John D. Hopkins ,  Richard J. Hill ,  Indra V. Chary ,  Kar Wui Thong

IPC: H01L23/535 ,  H01L27/11556 ,  H01L27/11582 ,  H01L21/768

Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers above a conductor tier. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers. The channel-material strings directly electrically couple with conductor material of the conductor tier by conducting material that is in a lowest of the conductive tiers and that is directly against multiple of the channel-material strings. The channel-material strings in the laterally-spaced memory blocks comprise part of a memory plane. A wall in the lowest conductive tier is aside the conducting material. The wall is in a region that is edge-of-plane relative to the memory plane. The edge-of-plane region comprises a TAV region. The wall is horizontally-elongated relative to an edge of the TAV region that is in the edge-of-plane region. Other memory arrays and methods are disclosed.

公开(公告)号：US20230052332A1

公开(公告)日：2023-02-16

申请号：US17398188

申请日：2021-08-10

Applicant: Micron Technology, Inc.

Inventor： Alyssa N. Scarbrough ,  M. Jared Barclay ,  John D. Hopkins ,  Jordan D. Greenlee

IPC: H01L23/535 ,  H01L27/11556 ,  H01L27/11582 ,  H01L21/768

Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers above a conductor tier. The conductor tier is directly above a lower tier that comprises conductive lines that are horizontally elongated. An insulator tier is vertically between the conductor tier and the lower tier. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers. The channel-material strings directly electrically couple to the conductor material of the conductor tier. A through-array-via (TAV) region comprises TAVs that individually directly electrically couple to one of the conductive lines. Insulator walls are in the TAV region. The insulator walls extend vertically through the conductor tier and the insulator tier to the lower tier and are horizontally elongated. Methods are also disclosed.

公开(公告)号：US11552090B2

公开(公告)日：2023-01-10

申请号：US17068470

申请日：2020-10-12

Applicant: Micron Technology, Inc.

Inventor： Daniel Billingsley ,  Jordan D. Greenlee ,  John D. Hopkins ,  Yongjun Jeff Hu ,  Swapnil Lengade

IPC: H01L27/11582 ,  H01L27/11556 ,  G11C16/04 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11524

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming an upper stack directly above a lower stack. The lower stack comprises vertically-alternating lower-first-tiers and lower-second-tiers. The upper stack comprises vertically-alternating upper-first-tiers and upper-second-tiers. Lower channel openings extend through the lower-first-tiers and the lower-second-tiers. The lower channel openings have sacrificial material therein. An upper of the lower-second-tiers or a lower of the upper-second-tiers comprises non-stoichiometric silicon dioxide that has a silicon-to-oxygen atomic ratio greater than 0.5. A higher of the upper-second-tiers that is above said lower upper-second-tier comprises silicon dioxide that has a silicon-to-oxygen atomic ratio less than or equal to 0.5. Upper channel openings are etched through the upper-first-tiers and the upper-second-tiers to stop on said upper lower-second-tier or said lower upper-second-tier. After the stop, the sacrificial material is removed from the lower channel openings and channel-material strings are formed in the upper and lower channel openings. Other embodiments, including structure independent of method, are disclosed.

公开(公告)号：US20220359565A1

公开(公告)日：2022-11-10

申请号：US17867501

申请日：2022-07-18

Applicant: Micron Technology, Inc.

Inventor： John D. Hopkins ,  Shyam Surthi ,  Jordan D. Greenlee

IPC: H01L27/11582 ,  H01L29/49 ,  H01L29/51 ,  H01L21/28 ,  H01L29/792 ,  H01L29/788 ,  H01L21/02 ,  H01L27/11556

Abstract: Some embodiments include a NAND memory array having a vertical stack of alternating insulative levels and conductive levels. The conductive levels include terminal regions, and include nonterminal regions proximate the terminal regions. The terminal regions are vertically thicker than the nonterminal regions, and are configured as segments which are vertically stacked one atop another and which are vertically spaced from one another. Blocks are adjacent to the segments and have approximately a same vertical thickness as the segments. The blocks include high-k dielectric material, charge-blocking material and charge-storage material. Channel material extends vertically along the stack and is adjacent to the blocks. Some embodiments include integrated assemblies. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20220320129A1

公开(公告)日：2022-10-06

申请号：US17223359

申请日：2021-04-06

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  John D. Hopkins

IPC: H01L27/11556 ,  H01L21/768 ,  H01L27/11582

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a conductor tier comprising conductor material on a substrate. Laterally-spaced memory-block regions are formed that individually comprise a vertical stack comprising alternating first tiers and second tiers directly above the conductor tier. Channel-material strings of memory cells extend through the first tiers and the second tiers. Horizontally-elongated lines are formed in the conductor tier between the laterally-spaced memory-block regions. The horizontally-elongated lines are of different composition from an upper portion of the conductor material and comprise metal material. After the horizontally-elongated lines are formed, conductive material is formed in a lower of the first tiers and that directly electrically couples together the channel material of individual of the channel-material strings and the conductor material of the conductor tier. Other embodiments, including structure independent of method, are disclosed.

公开(公告)号：US20220320128A1

公开(公告)日：2022-10-06

申请号：US17223254

申请日：2021-04-06

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  Alyssa N. Scarbrough ,  John D. Hopkins

IPC: H01L27/11556 ,  H01L27/11582 ,  G11C5/06

Abstract: Some embodiments include an integrated assembly having a memory region and another region adjacent the memory region. Channel-material-pillars are arranged within the memory region, and conductive posts are arranged within said other region. A source structure is coupled to lower regions of the channel-material-pillars. A panel extends across the memory region and said other region, and separates a first memory-block-region from a second memory-block-region. Doped-semiconductor-material is directly adjacent to the panel within the memory region and the other region. Rings laterally surround lower regions of the conductive posts. The rings are between the conductive posts and the doped-semiconductor-material. The rings include laminates of two or more materials, with at least one of said two or more materials being insulative. Some embodiments include methods for forming integrated assemblies.

公开(公告)号：US20220199646A1

公开(公告)日：2022-06-23

申请号：US17692041

申请日：2022-03-10

Applicant: Micron Technology, Inc.

Inventor： John D. Hopkins ,  Jordan D. Greenlee

IPC: H01L27/11582 ,  H01L23/528 ,  H01L27/11556 ,  H01L23/532 ,  H01L21/02 ,  H01L21/311 ,  H01L21/28 ,  H01L27/11565 ,  H01L27/11519

Abstract: Some embodiments include a memory device having a vertical stack of alternating insulative levels and conductive levels. The conductive levels include first regions, and include second regions laterally adjacent to the first regions. The first regions have a first vertical thickness and at least two different metal-containing materials along the first vertical thickness. The second regions have a second vertical thickness at least as large as the first vertical thickness, and have only a single metal-containing material along the second vertical thickness. Dielectric-barrier material is laterally adjacent to the first regions. Charge-blocking material is laterally adjacent to the dielectric-barrier material. Charge-storage material is laterally adjacent to the charge-blocking material. Dielectric material is laterally adjacent to the charge storage material. Channel material is laterally adjacent to the dielectric material.

公开(公告)号：US20220199640A1

公开(公告)日：2022-06-23

申请号：US17126777

申请日：2020-12-18

Applicant: Micron Technology, Inc.

Inventor： John D. Hopkins ,  Jordan D. Greenlee

IPC: H01L27/11582 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11575 ,  H01L27/11573

Abstract: Some embodiments include an integrated assembly having a first memory region, a second memory region, and an intermediate region between the first and second memory regions. The intermediate region has a first edge proximate the first memory region and has a second edge proximate the second memory region. Channel-material-pillars are arranged within the first and second memory regions. Conductive posts are arranged within the intermediate region. Doped-semiconductor-material is within the intermediate region and is configured as a substantially H-shaped structure having a first leg region along the first edge, a second leg region along the second edge, and a belt region adjacent the panel. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20220199637A1

公开(公告)日：2022-06-23

申请号：US17125200

申请日：2020-12-17

Applicant: Micron Technology, Inc.

Inventor： Shuangqiang Luo ,  John D. Hopkins ,  Lifang Xu ,  Nancy M. Lomeli ,  Indra V. Chary ,  Kar Wui Thong ,  Shicong Wang

IPC: H01L27/11556 ,  H01L27/11582 ,  G11C5/06 ,  G11C5/02 ,  H01L21/768

Abstract: A microelectronic device comprises a stack structure comprising a vertically alternating sequence of conductive material and insulative material arranged in tiers. The stack structure has blocks separated from one another by first dielectric slot structures. Each of the blocks comprises two crest regions, a stadium structure interposed between the two crest regions in a first horizontal direction and comprising opposing staircase structures each having steps comprising edges of the tiers of the stack structure, and two bridge regions neighboring opposing sides of the stadium structure in a second horizontal direction orthogonal to the first horizontal direction and having upper surfaces substantially coplanar with upper surfaces of the two crest regions. At least one second dielectric slot structure is within horizontal boundaries of the stadium structure in the first horizontal direction and partially vertically extends through and segmenting each of the two bridge regions. Memory devices, electronic systems, and methods of forming microelectronic devices are also described.

公开(公告)号：US20220165742A1

公开(公告)日：2022-05-26

申请号：US17670685

申请日：2022-02-14

Applicant: Micron Technology, Inc.

Inventor： John D. Hopkins ,  Alyssa N. Scarbrough

IPC: H01L27/11556 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11582

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a lower portion of a stack that will comprise vertically-alternating first tiers and second tiers on a substrate. The stack comprises laterally-spaced memory-block regions, Material of the first tiers is of different composition from material of the second tiers. Horizontally-elongated lines are formed in the lower portion that are individually between immediately-laterally-adjacent of the memory-block regions. The lines comprise sacrificial material. The lines individually comprise laterally-opposing projections longitudinally therealong in a lowest of the first tiers. The vertically-alternating first tiers and second tiers of an upper portion of the stack are formed above the lower portion and the lines, and channel-material strings are formed that extend through the first tiers and the second tiers in the upper portion to the lower portion. Horizontally-elongated trenches are formed into the stack that are individually between the immediately-laterally-adjacent memory-block regions and extend to the line there-between. The sacrificial material of the lines and projections is removed through the trenches. Intervening material is formed in the trenches and void-spaces left as a result of the removing of the sacrificial material of the lines. Other embodiments are disclosed.