公开(公告)号：US11257962B2

公开(公告)日：2022-02-22

申请号：US16401844

申请日：2019-05-02

Applicant: Micron Technology, Inc.

Inventor： Yunfei Gao ,  Kamal M. Karda ,  Stephen J. Kramer ,  Gurtej S. Sandhu ,  Sumeet C. Pandey ,  Haitao Liu

IPC: H01L29/786 ,  G11C13/00 ,  H01L29/16 ,  H01L51/05

Abstract: A transistor comprises a channel region between a source region and a drain region, a dielectric material adjacent to the channel region, an electrode adjacent to the dielectric material, and an electrolyte between the dielectric material and the electrode. Related semiconductor devices comprising at least one transistors, related electronic systems, and related methods are also disclosed.

公开(公告)号：US20220028903A1

公开(公告)日：2022-01-27

申请号：US16934607

申请日：2020-07-21

Applicant: Micron Technology, Inc.

Inventor： Yi Fang Lee ,  Jaydip Guha ,  Lars P. Heineck ,  Kamal M. Karda ,  Si-Woo Lee ,  Terrence B. McDaniel ,  Scott E. Sills ,  Kevin J. Torek ,  Sheng-Wei Yang

IPC: H01L27/12 ,  H01L21/84

Abstract: An array of vertical transistors comprises spaced pillars of individual vertical transistors that individually comprise an upper source/drain region, a lower source/drain region, and a channel region vertically there-between. The upper source/drain region comprises a conductor oxide material in individual of the pillars. The channel region comprises an oxide semiconductor material in the individual pillars. The lower source/drain region comprises a first conductive oxide material in the individual pillars atop and directly against a second conductive oxide material in the individual pillars. Horizontally-elongated and spaced conductor lines individually interconnect a respective multiple of the vertical transistors in a column direction. The conductor lines individually comprise the second conductive oxide material atop and directly against metal material. The first conductive oxide material, the second conductive oxide material, and the metal material comprise different compositions relative one another. The second conductive oxide material of the conductor lines is below and directly against the second conductive oxide material of the lower source/drain region of the individual pillars of the respective multiple vertical transistors. Horizontally-elongated and spaced conductive gate lines are individually operatively aside the oxide semiconductor material of the channel region of the individual pillars and individually interconnect a respective plurality of the vertical transistors in a row direction. A conductive structure is laterally-between and spaced from immediately-adjacent of the spaced conductor lines in the row direction. The conductive structures individually comprise a top surface that is higher than a top surface of the metal material of the conductor lines. Other embodiments, including method, are disclosed.

公开(公告)号：US11211487B2

公开(公告)日：2021-12-28

申请号：US16542078

申请日：2019-08-15

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Chandra Mouli ,  Haitao Liu

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/04 ,  H01L27/108 ,  H01L29/45 ,  H01L29/08 ,  H01L29/10 ,  H01L29/267

Abstract: Some embodiments include an integrated assembly having a semiconductor material with a more-doped region adjacent to a less-doped region. A two-dimensional material is between the more-doped region and a portion of the less-doped region. Some embodiments include an integrated assembly which contains a semiconductor material, a metal-containing material over the semiconductor material, and a two-dimensional material between a portion of the semiconductor material and the metal-containing material. Some embodiments include a transistor having a first source/drain region, a second source/drain region, a channel region between the first and second source/drain regions, and a two-dimensional material between the channel region and the first source; drain region.

公开(公告)号：US11170835B2

公开(公告)日：2021-11-09

申请号：US16011771

申请日：2018-06-19

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Chandra Mouli ,  Durai Vishak Nirmal Ramaswamy ,  F. Daniel Gealy

IPC: G11C11/22 ,  H01L29/788 ,  H01L29/423 ,  H01L29/78 ,  H01L27/1159 ,  H01L29/66

Abstract: A field effect transistor construction includes a semiconductive channel core. A source/drain region is at opposite ends of the channel core. A gate is proximate a periphery of the channel core. A gate insulator is between the gate and the channel core. The gate insulator has local regions radially there-through that have different capacitance at different circumferential locations relative to the channel core periphery. Additional constructions, and methods, are disclosed.

公开(公告)号：US20210143284A1

公开(公告)日：2021-05-13

申请号：US16682617

申请日：2019-11-13

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Haitao Liu

IPC: H01L29/786 ,  H01L29/66

Abstract: A microelectronic device comprises a conductive line and a transistor adjacent to the conductive line. The transistor comprises a channel material extending into the conductive line, the channel material contacting the conductive line in three dimensions, a dielectric material adjacent to the channel material, a conductive material adjacent to the dielectric material, and a passivation material adjacent to the channel material. The microelectronic device further comprises a conductive contact adjacent to the channel material, the conductive contact including a portion extending between opposing portions of the channel material. Related microelectronic devices, electronic devices, and related methods are also disclosed.

公开(公告)号：US10825816B2

公开(公告)日：2020-11-03

申请号：US15898086

申请日：2018-02-15

Applicant: Micron Technology, Inc.

Inventor： Yunfei Gao ,  Richard J. Hill ,  Gurtej S. Sandhu ,  Haitao Liu ,  Deepak Chandra Pandey ,  Srinivas Pulugurtha ,  Kamal M. Karda

IPC: H01L23/58 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L27/108 ,  H01L29/423 ,  H01L29/20 ,  H01L29/78 ,  H01L29/417 ,  H01L29/10 ,  H01L29/267

Abstract: A recessed access device comprises a conductive gate in a trench in semiconductor material. A gate insulator is along sidewalls and a base of the trench between the conductive gate and the semiconductor material. A pair of source/drain regions is in upper portions of the semiconductor material on opposing sides of the trench. A channel region is in the semiconductor material below the pair of source/drain regions along the trench sidewalls and around the trench base. At least some of the channel region comprises GaP.

公开(公告)号：US10756217B2

公开(公告)日：2020-08-25

申请号：US16132879

申请日：2018-09-17

Applicant: Micron Technology, Inc.

Inventor： Haitao Liu ,  Yunfei Gao ,  Kamal M. Karda ,  Deepak Chandra Pandey ,  Sanh D. Tang ,  Litao Yang

IPC: H01L29/786 ,  H01L29/78 ,  H01L27/088

Abstract: Systems, apparatuses and methods related to access devices formed with conductive contacts are described. An example apparatus may include an access device that includes a field-effect transistor (FET). A vertical pillar may be formed to include a channel of the FET, with a portion of the vertical pillar formed between at least two gates of the FET (i.e., a multi-gate Fin-FET). A conductive contact may be coupled to a body region of the vertical pillar.

公开(公告)号：US20190279986A1

公开(公告)日：2019-09-12

申请号：US16421286

申请日：2019-05-23

Applicant: Micron Technology, Inc.

Inventor： Gurtej S. Sandhu ,  Kamal M. Karda

IPC: H01L27/108

Abstract: Some embodiments include a memory cell having a transistor with a channel region between a first source/drain region and a second source/drain region. A controlled-conductivity region is adjacent the first source/drain region. The controlled-conductivity region has a low-conductivity mode and a high-conductivity mode. The high-conductivity mode has a conductivity at least 106 greater than a conductivity of the low-conductivity mode. The channel region includes a first material having a first bandgap, and the controlled-conductivity region includes a second material having a second bandgap which is greater than the first bandgap. A charge-storage device is electrically coupled to the first source/drain region through the controlled-conductivity region. A bitline is electrically coupled to the second source/drain region.

公开(公告)号：US10396082B2

公开(公告)日：2019-08-27

申请号：US15642148

申请日：2017-07-05

Applicant: Micron Technology, Inc.

Inventor： Gurtej S. Sandhu ,  Kamal M. Karda

IPC: H01L27/108

Abstract: Some embodiments include a memory cell having a transistor with a channel region between a first source/drain region and a second source/drain region. A controlled-conductivity region is adjacent the first source/drain region. The controlled-conductivity region has a low-conductivity mode and a high-conductivity mode. The high-conductivity mode has a conductivity at least 106 greater than a conductivity of the low-conductivity mode. The channel region includes a first material having a first bandgap, and the controlled-conductivity region includes a second material having a second bandgap which is greater than the first bandgap. A charge-storage device is electrically coupled to the first source/drain region through the controlled-conductivity region. A bitline is electrically coupled to the second source/drain region.

公开(公告)号：US20190189626A1

公开(公告)日：2019-06-20

申请号：US16284475

申请日：2019-02-25

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Qian Tao ,  Durai Vishak Nirmal Ramaswamy ,  Haitao Liu ,  Kirk D. Prall ,  Ashonita Chavan

IPC: H01L27/11502 ,  H01G4/008 ,  H01G4/40 ,  H01G4/33 ,  H01G4/08 ,  H01L49/02 ,  H01L27/11507 ,  H01L27/108

Abstract: A memory cell includes a select device and a capacitor electrically coupled in series with the select device. The capacitor includes two conductive capacitor electrodes having ferroelectric material there-between. The capacitor has an intrinsic current leakage path from one of the capacitor electrodes to the other through the ferroelectric material. There is a parallel current leakage path from the one capacitor electrode to the other. The parallel current leakage path is circuit-parallel the intrinsic path and of lower total resistance than the intrinsic path. Other aspects are disclosed.