公开(公告)号：US20240256382A1

公开(公告)日：2024-08-01

申请号：US18424342

申请日：2024-01-26

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Sujeet Ayyapureddi

IPC: G06F11/10

CPC classification number: G06F11/1076

Abstract: Apparatuses, systems, and methods for bounded fault compliant metadata storage. Memory devices include a first data terminal and a second data terminal. As part of an access operation a first set of data and a first set of metadata may be sent/received across the first terminal and a second set of data and a second set of metadata may be sent/received across the second terminal. The first set of metadata may be stored in a first location and the second set of metadata may be stored in a second location in the memory array, such as a first and second column plane. The two locations may be remote from each other.

公开(公告)号：US20240176699A1

公开(公告)日：2024-05-30

申请号：US18504234

申请日：2023-11-08

Applicant: Micron Technology, Inc.

Inventor： Sujeet Ayyapureddi ,  Scott E. Smith

IPC: G06F11/10

CPC classification number: G06F11/1068 ,  G06F11/1016

Abstract: Apparatuses, systems, and methods for enhanced metadata information. The memory array includes a number of column planes and an extra column plane. A memory device is set in an ×4 single-pass operational mode. In this mode, the memory may store a data codeword in a selected ones of the column planes, and metadata may be stored in a non-selected ones of the column planes and in the extra column plane. An error correction code circuit (ECC) may store parity bits associated with the data and metadata in the non-selected ones of the column planes. In this manner, the data, metadata, and parity may be accessed as part of a single access of the memory array.

公开(公告)号：US11996135B2

公开(公告)日：2024-05-28

申请号：US17543932

申请日：2021-12-07

Applicant: Micron Technology, Inc.

Inventor： Sujeet Ayyapureddi ,  Randall J. Rooney

IPC: G06F13/16 ,  G06F21/55 ,  G11C11/4078

CPC classification number: G11C11/4078 ,  G06F13/1605 ,  G06F13/1668 ,  G06F21/554 ,  G06F2221/034

Abstract: Memory devices, systems including memory devices, and methods of operating memory devices are described in which waterfall attacks can be prevented from degrading data by alerting a memory controller that the memory device requests time to perform internal management operations, and should not be sent any further commands (e.g., activate commands) for a predetermined amount of time. In one embodiment, a memory device includes an external pin, a mode register, a memory array including a plurality of rows of memory cells, and circuitry configured to: determine that a criterion to perform an internal management operation on a subset of the plurality of rows has been met, transmit, in response to determining the criterion has been met, a signal to the external pin, determine a duration corresponding to the internal management operation, and write a bit value indicative of the determined duration to the mode register.

公开(公告)号：US20240105251A1

公开(公告)日：2024-03-28

申请号：US17954176

申请日：2022-09-27

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Sujeet Ayyapureddi

IPC: G11C11/406

CPC classification number: G11C11/40618 ,  G11C11/40615

Abstract: An exemplary memory controller includes a refresh manager circuit configured to provide a refresh command to a memory system via a command and address bus to initiate a refresh operation at a bank of the memory system. In response to provision of the refresh command, the refresh manager circuit is further configured to issue a bank status command to the host to indicate that the bank of the memory system has switched to unavailable.

公开(公告)号：US20230393770A1

公开(公告)日：2023-12-07

申请号：US17946518

申请日：2022-09-16

Applicant: Micron Technology, Inc.

Inventor： Yang Lu ,  Sujeet Ayyapureddi ,  Edmund J. Gieske ,  Cagdas Dirik ,  Ameen D. Akel ,  Elliott C. Cooper-Balis ,  Amitava Majumdar ,  Robert M. Walker ,  Danilo Caraccio

IPC: G06F3/06

CPC classification number: G06F3/0632 ,  G06F3/0604 ,  G06F3/0679

Abstract: Systems, methods, and apparatus for memory device security and row hammer mitigation are described. A control mechanism may be implemented in a front-end and/or a back-end of a memory sub-system to refresh rows of the memory. A row activation command having a row address at control circuitry of a memory sub-system and incrementing a first count of a row counter corresponding to the row address stored in a content addressable memory (CAM) of the memory sub-system may be received. Control circuitry may determine whether the first count is greater than a row hammer threshold (RHT) minus a second count of a CAM decrease counter (CDC); the second count may be incremented each time the CAM is full. A refresh command to the row address may be issued when a determination is made that the first count is greater than the RHT minus the second count.

公开(公告)号：US20230206988A1

公开(公告)日：2023-06-29

申请号：US17965706

申请日：2022-10-13

Applicant: Micron Technology, Inc.

Inventor： Sujeet Ayyapureddi

IPC: G11C11/4078 ,  G11C11/4096 ,  G11C29/52

CPC classification number: G11C11/4078 ,  G11C11/4096 ,  G11C29/52

Abstract: Methods, apparatuses, and systems related to operations for memory process feedback. A controller can monitor memory activities, such as processes, identify row hammer aggressors, and perform mitigating steps to the row hammer aggressors. The controller may have a table of addresses of row hammer aggressors and perform operations of tracking row hammer aggressors. The controller can determine whether the number of aggressors reaches a threshold. When the number of aggressors reaches the threshold, the controller can send a message with the aggressor addresses to the operating system. The operating system can perform mitigating steps to the row hammer aggressors. In some embodiments, the controller may identify the row hammer aggressors and inject poisoned data into the process to mitigate the row hammer aggressors.

公开(公告)号：US11562784B2

公开(公告)日：2023-01-24

申请号：US16994408

申请日：2020-08-14

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Sujeet Ayyapureddi

IPC: G11C5/14 ,  G06F7/58 ,  G11C11/408 ,  H03M1/12

Abstract: Apparatuses, systems, and methods for voltage based random number generation. A memory may include a number of different voltages, which may be used to power various operations of the memory. During access operations to the memory, the voltage may vary, for example as word lines of the memory are accessed. The variability of the voltage may represent a source of randomness and unpredictability in the memory. A random number generator may provide a random number based on the voltage. For example, an analog to binary converter (ADC) may generate a binary number based on the voltage, and the random number may be based on the binary number.

公开(公告)号：US20220408886A1

公开(公告)日：2022-12-29

申请号：US17822918

申请日：2022-08-29

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Sujeet Ayyapureddi ,  Henry Michael Lubowe ,  Edison Tam King Miguel ,  Matthew Joseph Kane ,  Jr-Jay Jhang ,  Jens Mitchell Nielsen ,  Cédric Eric Jean-Edouard Bernard ,  Brian Dennis Paschke ,  Junyong Park ,  Mark Woodhiser Huang ,  Stephanie Lydia Renee Choplin

IPC: A44C5/14 ,  A44C5/00

Abstract: Apparatuses, systems, and methods for memory module data drives. A memory module includes a number of memory devices as well as module logic. Each memory device provides data by driving voltages along a data bus with a data bus driver of the memory device. An output driver, which is located on the module logic receives the voltages along the data bus and drives voltages of an external data terminal to output the data. The output driver may have a greater drive strength than the data bus driver.

公开(公告)号：US20220293166A1

公开(公告)日：2022-09-15

申请号：US17201941

申请日：2021-03-15

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Sujeet Ayyapureddi ,  Donald M. Morgan

IPC: G11C11/406 ,  G11C11/408 ,  G11C29/44 ,  G11C29/42

Abstract: Apparatuses, systems, and methods for sketch circuits for refresh binning. The rows of a memory may have different information retention times. The row addresses may be sorted into different bins based on these information retention times. In order to store information about which row addresses are associated with which bins a sketch circuit may be used. When an address is generated as part of a refresh operation, it may be used to generate a number of different hash values, which may be used to index entries in a storage structure. The entries may indicate which bin the address is associated with. Based on the binning information, the memory may refresh the address at different rates (e.g., by determining whether to provide the address as a refresh address or not).

公开(公告)号：US20220223596A1

公开(公告)日：2022-07-14

申请号：US17144300

申请日：2021-01-08

Applicant: Micron Technology, Inc.

Inventor： Sujeet Ayyapureddi

IPC: H01L27/108 ,  H01L27/12 ,  H01L49/02 ,  H01L29/786

Abstract: Systems, methods and apparatus are provided for decoupling capacitors for an array of vertically stacked memory cells. Embodiments provide that the decoupling capacitors are electrically coupled to a power bus.