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    GANGED READ OPERATION FOR MULTIPLE SUB-BLOCKS
    31.
    发明申请
    GANGED READ OPERATION FOR MULTIPLE SUB-BLOCKS 有权

    公开(公告)号：US20250104779A1

    公开(公告)日：2025-03-27

    申请号：US18782517

    申请日：2024-07-24

    Applicant: Micron Technology, Inc.

    Inventor： Yu-Chung Lien ,  Ting Luo ,  Zhenming Zhou

    IPC: G11C16/26 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/34

    Abstract: Methods, systems, and devices for a ganged read operation for multiple sub-blocks are described. The method may include writing a respective first logic state to each memory cell of a set of memory portions and biasing a first word line and a second word line to a first voltage. In some examples, the first word line may correspond to a first memory portion and the second word line may correspond to a second memory portion. Further, the method may include applying a first read pulse to the first word line and a second read pulse to the second word line and reading a second logic state from one or more memory cells of the first memory portion and the second memory portion. Further, the method may include validating the write operation based on reading the second logic state from the memory cells of the first memory portion and the second memory portion.

    CHARGE LOSS MITIGATION THROUGH DYNAMIC PROGRAMMING SEQUENCE
    32.
    发明申请
    CHARGE LOSS MITIGATION THROUGH DYNAMIC PROGRAMMING SEQUENCE 有权

    公开(公告)号：US20250094063A1

    公开(公告)日：2025-03-20

    申请号：US18968924

    申请日：2024-12-04

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Yu-Chung Lien ,  Zhenming Zhou

    IPC: G06F3/06

    Abstract: A program command specifying new data to be programmed is received and partitioned into a plurality of data partitions. A wordline addressing a first set of memory cells to be programmed with a data partition of the plurality of data partitions is identified for a specified block of the memory device. Existing data stored by a second set of memory cells is read. An expected data state metrics is produced for each data partition of the plurality of data partitions. A data partition associated with a lowest expected data state metric among the plurality of expected data state metrics is identified. The identified data partition is programmed to the identified wordline.

    Management of dynamic read voltage sequences in a memory subsystem
    33.
    发明授权
    Management of dynamic read voltage sequences in a memory subsystem 有权

    公开(公告)号：US12237003B2

    公开(公告)日：2025-02-25

    申请号：US17881180

    申请日：2022-08-04

    Applicant: Micron Technology, Inc.

    Inventor： Yu-Chung Lien ,  Zhenming Zhou

    IPC: G11C16/04 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4096

    Abstract: A memory subsystem receives a first read command and a second read command. Responsive to determining that the first read command originated from a host system, the memory subsystem selects a reverse read trim setting. Responsive to determining that the second read command did not originate from the host system, the memory subsystem selects a forward read trim setting. The memory subsystem executes the first read command using the reverse read trim setting. The memory subsystem executes the second read command using the forward read trim setting.

    MANAGING ALLOCATION OF BLOCKS ACROSS PLANES IN A MEMORY SUB-SYSTEM
    34.
    发明申请
    MANAGING ALLOCATION OF BLOCKS ACROSS PLANES IN A MEMORY SUB-SYSTEM 有权

    公开(公告)号：US20250006270A1

    公开(公告)日：2025-01-02

    申请号：US18753662

    申请日：2024-06-25

    Applicant: Micron Technology, Inc.

    Inventor： Yu-Chung Lien ,  Aaron Lee ,  Zhenming Zhou

    IPC: G11C16/10 ,  G11C16/08 ,  G11C29/52

    Abstract: A processing device, operatively coupled with a memory device, performs a first programming operation on a first set of cells addressable by a first wordline of a first plane of the memory device. The processing device identifies a predefined index shift value associated with the first wordline. The processing device determines, by applying the predefined index shift value to a first index value of the first wordline, a second index value of a second wordline of a second plane of the memory device. The processing device further performs a second programming operation on a second set of cells addressable by the second wordline of the second plane.

    Adaptive error avoidance in the memory devices
    36.
    发明授权
    Adaptive error avoidance in the memory devices 有权

    公开(公告)号：US12073905B2

    公开(公告)日：2024-08-27

    申请号：US17894528

    申请日：2022-08-24

    Applicant: Micron Technology, Inc.

    Inventor： Li-Te Chang ,  Yu-Chung Lien ,  Murong Lang ,  Zhenming Zhou ,  Michael G. Miller

    IPC: G11C29/52 ,  G11C16/08 ,  G11C16/10 ,  G11C16/34

    CPC classification number: G11C29/52 ,  G11C16/08 ,  G11C16/102 ,  G11C16/3404

    Abstract: An example method of performing memory access operations comprises: receiving a request to perform a memory access operation with respect to a set of memory cells connected to a wordline of a memory device; identifying a block family associated with the set of memory cells; determining, for each logical programming level of a plurality of logical programming levels, a corresponding default block family error avoidance (BFEA) threshold voltage offset value associated with the block family; determining a value of a data state metric associated with the set of memory cells; responsive to determining that the value of the data state metric satisfies a threshold criterion, determining, for each logical programming level of a plurality of logical programming levels, a corresponding sub-BFEA threshold voltage offset value; and performing the memory access operation by applying, for each logical programming level of the plurality of logical programming levels, a combination of the default BFEA threshold voltage value, the sub-BFEA threshold voltage value, and a corresponding base voltage level.

    PASS VOLTAGE ADJUSTMENT FOR PROGRAM OPERATION IN A MEMORY DEVICE
    38.
    发明公开
    PASS VOLTAGE ADJUSTMENT FOR PROGRAM OPERATION IN A MEMORY DEVICE 审中-公开

    公开(公告)号：US20240203513A1

    公开(公告)日：2024-06-20

    申请号：US18528178

    申请日：2023-12-04

    Applicant: Micron Technology, Inc.

    Inventor： Yu-Chung Lien ,  Zhenming Zhou

    IPC: G11C16/34 ,  G11C16/10 ,  G11C29/02

    CPC classification number: G11C16/3459 ,  G11C16/102 ,  G11C16/3495 ,  G11C29/022

    Abstract: A request to perform a program operation on a set of vertically stacked memory cells of a memory device is received. A pass voltage adjustment value based on a number of program erase cycles (PECs) associated with the memory device is determined responsive to determining that at least one memory cell of the set of vertically stacked memory cells is non-programmable. A default pass voltage is adjusted by the pass voltage adjustment value to generate an adjusted pass voltage. The program operation on the set of vertically stacked memory cells is performed using the adjusted pass voltage.

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