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    Half block management for flash storage devices
    35.
    发明授权
    Half block management for flash storage devices 有权
    闪存存储设备的半块管理

    公开(公告)号：US09558108B2

    公开(公告)日：2017-01-31

    申请号：US14018149

    申请日：2013-09-04

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Yu-Ming Chang ,  Yung-Chun Li ,  Hsing-Chen Lu ,  Hsiang-Pang Li ,  Cheng-Yuan Wang ,  Yuan-Hao Chang ,  Tei-Wei Kuo

    IPC: G06F12/00 ,  G06F12/02 ,  G11C16/34 ,  G11C16/04 ,  G11C16/16

    CPC classification number: G06F12/0246 ,  G06F2212/7205 ,  G11C16/0483 ,  G11C16/16 ,  G11C16/3427

    Abstract: A method for managing block erase operations is provided for an array of memory cells including erasable blocks of memory cells in the array. The method comprises maintaining status data for a plurality of sub-blocks of the erasable blocks of the array. The status data indicate whether the sub-blocks are currently accessible and whether the sub-blocks are invalid. The method comprises, in response to a request to erase a selected sub-block of a particular erasable block, issuing an erase command to erase the particular block if the other sub-blocks of the particular erasable block are invalid, else updating the status data to indicate that the selected sub-block is invalid.

    Abstract translation: 提供了一种用于管理块擦除操作的方法，用于包括阵列中的可擦除存储单元块的存储单元阵列。 该方法包括维护阵列的可擦除块的多个子块的状态数据。 状态数据指示子块当前是否可访问以及子块是否无效。 该方法响应于擦除特定可擦除块的所选子块的请求，如果特定可擦除块的其他子块无效则发出擦除命令以擦除特定块，否则更新状态数据 以指示所选择的子块是无效的。

    Heal leveling
    36.
    发明授权
    Heal leveling 有权
    治愈

    公开(公告)号：US09348748B2

    公开(公告)日：2016-05-24

    申请号：US14578820

    申请日：2014-12-22

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Yu-Ming Chang ,  Hsiang-Pang Li ,  Hang-Ting Lue ,  Yuan-Hao Chang ,  Tei-Wei Kuo

    IPC: G06F12/00 ,  G06F12/02 ,  G11C29/44 ,  G11C16/34

    CPC classification number: G06F12/0246 ,  G06F12/00 ,  G06F2212/1036 ,  G06F2212/7211 ,  G11C16/3495 ,  G11C29/4401

    Abstract: Technology is described that increases endurance of memory devices through heal leveling. Heal leveling is a lightweight solution to distribute healing cycles among memory blocks. Approaches described herein can accomplish heal leveling without introducing a large amount of overhead. Heal leveling significantly improves the access performance and the effective lifetime of memory blocks. By more evenly distributing the heal count it may not be necessary to directly apply wear leveling based on access counts of each block because each block will be more evenly accessed in the long run. Heal leveling may be performed by moving data that is seldom or never modified after creation, such as read-only files, to blocks having suffered the greatest number, or a high number, of healing cycles.

    Abstract translation: 技术被描述为通过愈合平整来增加记忆装置的耐久性。 治疗矫正是一种轻量级的解决方案，可以在内存块之间分配愈合周期。 本文描述的方法可以在不引入大量开销的情况下完成愈合平整。 愈合程度显着提高了存储块的访问性能和有效寿命。 通过更均匀地分配治疗计数，可能不需要基于每个块的访问计数来直接应用磨损均衡，因为长期来看每个块将被更均匀地访问。 可以通过将创建后很少或从不修改的数据（例如只读文件）移动到遭受最大数量的块或大量愈合周期来执行愈合调平。

    Operation method for memory device
    37.
    发明授权
    Operation method for memory device 有权
    存储设备的操作方法

    公开(公告)号：US09305638B1

    公开(公告)日：2016-04-05

    申请号：US14526560

    申请日：2014-10-29

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Yu-Ming Chang ,  Yung-Chun Li ,  Chih-Chang Hsieh ,  Shih-Fu Huang ,  Hsiang-Pang Li ,  Yuan-Hao Chang ,  Tei-Wei Kuo

    IPC: G11C16/04 ,  G11C11/56 ,  G11C16/34

    CPC classification number: G11C11/5628 ,  G11C7/1006 ,  G11C11/5642 ,  G11C16/3427 ,  G11C16/3459 ,  G11C2211/5621 ,  G11C2211/5648

    Abstract: Operation methods for a memory device is provided. An operation method for the memory device comprises programming the memory device as described in follows. Data are provided. The data comprise a plurality of codes. Each number of the codes is counted. Then, a mapping rule is generated according to each number of the codes. In the mapping rule, each of the codes is mapped to one of a plurality of verifying voltage levels which are sequentially arranged from low to high. After that, the data are programmed into the memory device according to the mapping rule.

    Abstract translation: 提供了存储器件的操作方法。 存储器件的操作方法包括如下所述对存储器件进行编程。 提供数据。 数据包括多个代码。 每个代码数都被计数。 然后，根据代码的数量生成映射规则。 在映射规则中，每个代码被映射到从低到高顺序排列的多个验证电压电平之一。 之后，根据映射规则将数据编程到存储设备中。

    Memory device and operation method thereof
    38.
    发明授权
    Memory device and operation method thereof 有权

    公开(公告)号：US12056361B2

    公开(公告)日：2024-08-06

    申请号：US17814888

    申请日：2022-07-26

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Wei-Chen Wang ,  Tse-Yuan Wang ,  Yuan-Hao Chang ,  Tei-Wei Kuo

    IPC: G06F12/00 ,  G06F3/06

    CPC classification number: G06F3/0613 ,  G06F3/0644 ,  G06F3/0679

    Abstract: An embodiment of the present disclosure discloses a memory device. The memory device comprises a memory controller, a buffer and a memory array. The buffer is coupled to the memory controller or embedded in the memory controller. A storage space of the buffer is configured by the memory controller to include a plurality of groups. The memory array is coupled to the memory controller, and comprising a plurality of tiles. The groups are one-to-one corresponding to the tiles. Each of the groups is configured to store data to be written into the corresponding tile. The memory controller performs one or more write operations based on the groups.

    Neural network computation method using adaptive data representation
    39.
    发明授权
    Neural network computation method using adaptive data representation 有权

    公开(公告)号：US11594277B2

    公开(公告)日：2023-02-28

    申请号：US17871811

    申请日：2022-07-22

    Applicant: MACRONIX International Co., Ltd.

    Inventor： Shu-Yin Ho ,  Hsiang-Pang Li ,  Yao-Wen Kang ,  Chun-Feng Wu ,  Yuan-Hao Chang ,  Tei-Wei Kuo

    IPC: G11C11/54 ,  G06N3/06 ,  G06N3/08 ,  G06F7/544 ,  G11C11/4091 ,  G11C11/408 ,  G11C11/4094

    Abstract: A method for neural network computation using adaptive data representation, adapted for a processor to perform multiply-and-accumulate operations on a memory having a crossbar architecture, is provided. The memory comprises multiple input and output lines crossing each other, multiple cells respectively disposed at intersections of the input and output lines, and multiple sense amplifiers respectively connected to the output lines. In the method, an input cycle of kth bits respectively in an input data is adaptively divided into multiple sub-cycles, wherein a number of the divided sub-cycles is determined according to a value of k. The kth bits of the input data are inputted to the input lines with the sub-cycles and computation results of the output lines are sensed by the sense amplifiers. The computation results sensed in each sub-cycle are combined to obtain the output data corresponding to the kth bits of the input data.

    NEURAL NETWORK COMPUTATION METHOD USING ADAPTIVE DATA REPRESENTATION
    40.
    发明申请
    NEURAL NETWORK COMPUTATION METHOD USING ADAPTIVE DATA REPRESENTATION 有权

    公开(公告)号：US20220359003A1

    公开(公告)日：2022-11-10

    申请号：US17871811

    申请日：2022-07-22

    Applicant: MACRONIX International Co., Ltd.

    Inventor： Shu-Yin Ho ,  Hsiang-Pang Li ,  Yao-Wen Kang ,  Chun-Feng Wu ,  Yuan-Hao Chang ,  Tei-Wei Kuo

    IPC: G11C11/54 ,  G11C11/4091 ,  G11C11/408 ,  G06N3/06 ,  G06N3/08 ,  G06F7/544 ,  G11C11/4094

    Abstract: A method for neural network computation using adaptive data representation, adapted for a processor to perform multiply-and-accumulate operations on a memory having a crossbar architecture, is provided. The memory comprises multiple input and output lines crossing each other, multiple cells respectively disposed at intersections of the input and output lines, and multiple sense amplifiers respectively connected to the output lines. In the method, an input cycle of kth bits respectively in an input data is adaptively divided into multiple sub-cycles, wherein a number of the divided sub-cycles is determined according to a value of k. The kth bits of the input data are inputted to the input lines with the sub-cycles and computation results of the output lines are sensed by the sense amplifiers. The computation results sensed in each sub-cycle are combined to obtain the output data corresponding to the kth bits of the input data.

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