公开(公告)号：US20130069278A1

公开(公告)日：2013-03-21

申请号：US13424427

申请日：2012-03-20

申请人： Sachiko Kobayashi ,  Kazuhiro Takahata ,  Yingkang Zhang ,  Masafumi Asano ,  Shigeki Nojima

发明人： Sachiko Kobayashi ,  Kazuhiro Takahata ,  Yingkang Zhang ,  Masafumi Asano ,  Shigeki Nojima

IPC分类号： B29C67/00

CPC分类号： B29C59/026 ,  B29C59/002 ,  B29C71/04 ,  B29K2105/246 ,  B82Y10/00 ,  B82Y40/00 ,  G03F7/0002

摘要： According to one embodiment, a pattern formation device that presses a template that includes a concave and convex part onto a transferring object and that forms a pattern in which a shape of the concave and convex part is transferred is provided. The device includes: a calculation part; an adjustment part; and a transfer. The calculation part calculates, using design information of the pattern, the distribution of force applied to the pattern at a time of releasing the template pressed onto the transferring object from the transferring object. The adjustment part adjusts forming conditions of the pattern in order to uniformly approach the distribution of force calculated by the calculation part. The transfer part transfers the shape of the concave and convex part to the transferring object according to the forming conditions adjusted by the adjustment part.

摘要翻译： 根据一个实施例，提供了一种图案形成装置，其将包括凹凸部分的模板按压到转印体上并形成其中转移了凹凸部分的形状的图案。 该装置包括：计算部分; 调整部分; 和转移。 所述计算部使用所述图案的设计信息，计算从所述转印体上释放压印在所述转印体上的所述模板时施加到所述图案的力的分布。 调整部调整图案的成形条件，以均匀地接近由计算部计算出的力的分布。 转印部件根据由调节部件调整的成形条件将凹凸部的形状转印到转印体上。

公开(公告)号：US08230379B2

公开(公告)日：2012-07-24

申请号：US11874601

申请日：2007-10-18

申请人： Sachiko Kobayashi ,  Suigen Kyoh

发明人： Sachiko Kobayashi ,  Suigen Kyoh

IPC分类号： G06F17/32

CPC分类号： G06F17/5081

摘要： A design layout generating method for generating a design pattern of a semiconductor integrated circuit is disclosed. This method comprises modifying a first modification area extracted from a design layout by a first modifying method, and modifying a second modification area extracted from the design layout so as to include the first modification area by a second modifying method on the basis of a pattern modifying guideline calculated from at least a partial design layout in the second modification area.

摘要翻译： 公开了一种用于产生半导体集成电路的设计图案的设计布局生成方法。 该方法包括：通过第一修改方法修改从设计布局提取的第一修改区域，以及修改从设计布局提取的第二修改区域，以便通过基于模式修改的第二修改方法来包括第一修改区域 从第二修改区域中的至少部分设计布局计算出的准则。

公开(公告)号：US07530049B2

公开(公告)日：2009-05-05

申请号：US11440086

申请日：2006-05-25

申请人： Sachiko Kobayashi ,  Toshiya Kotani

发明人： Sachiko Kobayashi ,  Toshiya Kotani

IPC分类号： G06F17/50

CPC分类号： G03F1/68 ,  G03F1/36

摘要： A mask manufacturing system and a mask data creating method reusing data for processing information and environment in the past to reduce a photomask developing period, and a manufacturing method of a semiconductor device are disclosed. According to one aspect of the present invention, it is provided a mask manufacturing system comprising a storage device storing processing data for semiconductor integrated circuits processed in the past, a plurality of operation processing modules, a module selecting section selecting at least one operation processing modules, an optical proximity effect correction section executing optical proximity effect correction to a processing object data and generating a correction data by utilizing past correction information applied for a stored data equivalent to the processing object data, a converting section converting the processing object data into mask data, and a drawing system drawing a mask pattern based on the mask data.

摘要翻译： 掩模制造系统和掩模数据创建方法重复利用用于处理信息和环境的数据以减少光掩模生长期，以及半导体器件的制造方法。 根据本发明的一个方面，提供了一种掩模制造系统，包括存储用于过去处理的半导体集成电路的处理数据的存储装置，多个操作处理模块，模块选择部分，其选择至少一个操作处理模块 光学接近效应校正部分，对处理对象数据执行光学邻近效应校正，并通过利用应用于与处理对象数据相当的存储数据的过去校正信息产生校正数据;转换部分，将处理对象数据转换成掩模数据 以及基于掩模数据绘制掩模图案的绘图系统。

公开(公告)号：US07065739B2

公开(公告)日：2006-06-20

申请号：US10331005

申请日：2002-12-27

申请人： Sachiko Kobayashi ,  Toshiya Kotani ,  Satoshi Tanaka ,  Susumu Watanabe ,  Mitsuhiro Yano

发明人： Sachiko Kobayashi ,  Toshiya Kotani ,  Satoshi Tanaka ,  Susumu Watanabe ,  Mitsuhiro Yano

IPC分类号： G06F17/50 ,  G03F1/00

CPC分类号： G03F1/36 ,  G03F7/70441

摘要： A pattern correction method executed by a computer includes a first correction and a second correction. The first correction is executed by calculating a correction value, in consideration for an optical proximity effect, for edges (first edges) meeting a condition among the edges constituting a designed pattern. Subsequently, The second correction is executed for an edge (second edge) which does not meet the condition, by use of the correction value of any one of the edges (first edges) adjacent to the second edge among the first edges for which the first correction is executed, thus connecting the corrected first edge and the corrected second edge by a line segment. The pattern is corrected to a shape suitable for a mask drawing and a check with simple processing.

摘要翻译： 由计算机执行的图案校正方法包括第一校正和第二校正。 对于构成设计图案的边缘中满足条件的边缘（第一边缘），考虑光学邻近效应来计算校正值来执行第一校正。 随后，对于不符合条件的边缘（第二边缘），通过使用与第一边缘相邻的边缘（第一边缘）中的任何一个边缘（第一边缘）的第一边缘的第一边缘 执行校正，从而将校正的第一边缘和校正的第二边缘连接到线段。 该图案被校正为适于掩模绘图和具有简单处理的检查的形状。

公开(公告)号：US06964031B2

公开(公告)日：2005-11-08

申请号：US10255832

申请日：2002-09-27

申请人： Toshiya Kotani ,  Satoshi Tanaka ,  Soichi Inoue ,  Sachiko Kobayashi ,  Hirotaka Ichiakwa

发明人： Toshiya Kotani ,  Satoshi Tanaka ,  Soichi Inoue ,  Sachiko Kobayashi ,  Hirotaka Ichiakwa

IPC分类号： H01L21/027 ,  G03F1/00 ,  G03F1/36 ,  G06F17/50 ,  H01L21/00

CPC分类号： G03F1/36

摘要： A mask pattern generation method of generating a mask pattern from a designed pattern, comprising preparing the designed pattern, preparing a correction parameter, preparing a first correction library in which a plurality of pairs of an edge coordinate group and a correction value group to correct the edge coordinate group is registered, acquiring edge coordinate groups of the designed patterns, generating a second correction library in which only the plurality of pairs of an edge coordinate group agreeing with the acquired edge coordinate group and the correction value group is registered in the first correction library and simulation using the correction parameter, and correcting the designed pattern using the second correction library.

摘要翻译： 一种从设计图案生成掩模图案的掩模图案生成方法，包括准备设计图案，准备校正参数，准备第一校正库，其中多对边缘坐标组和校正值组校正第 登记边缘坐标组，获取所设计图案的边缘坐标组，生成第二校正库，其中在所述第一校正中仅登记与获取的边缘坐标组和校正值组一致的边缘坐标组的多对对 库和模拟，并使用第二校正库校正设计的模式。

公开(公告)号：US06110647A

公开(公告)日：2000-08-29

申请号：US024225

申请日：1998-02-17

申请人： Soichi Inoue ,  Hisashi Kaneko ,  Masahiko Hasunuma ,  Takamasa Usui ,  Masami Aoki ,  Kazuko Yamamoto ,  Sachiko Kobayashi

发明人： Soichi Inoue ,  Hisashi Kaneko ,  Masahiko Hasunuma ,  Takamasa Usui ,  Masami Aoki ,  Kazuko Yamamoto ,  Sachiko Kobayashi

IPC分类号： G03F9/00 ,  G03F1/36 ,  G03F1/68 ,  G03F7/00 ,  G03F7/20 ,  H01L21/027 ,  H01L21/768 ,  H01L21/82 ,  H01L21/822 ,  H01L27/04

CPC分类号： G03F7/70425 ,  G03F1/36 ,  G03F7/0035

摘要： A method of manufacturing a semiconductor device, comprises the steps of forming a first transfer pattern corresponding to a mask pattern on a major surface side of a semiconductor substrate through a first mask plate on which the first mask pattern having a straight portion and a bent portion is formed, and forming a second transfer pattern corresponding to a second mask pattern on a major surface side of the semiconductor substrate through a second mask plate on which the second mask pattern having a pattern arranged at a position corresponding to the straight portion is formed.

摘要翻译： 一种制造半导体器件的方法，包括以下步骤：通过第一掩模板在半导体衬底的主表面侧上形成与掩模图案对应的第一转印图案，其中第一掩模图案具有直的部分和弯曲部分 并且通过第二掩模板在半导体衬底的主表面侧上形成与第二掩模图案相对应的第二传输图案，在第二掩模板上形成布置在对应于直线部分的位置处的图案的第二掩模图案。

公开(公告)号：US08261217B2

公开(公告)日：2012-09-04

申请号：US12020275

申请日：2008-01-25

申请人： Sachiko Kobayashi

发明人： Sachiko Kobayashi

IPC分类号： G06F17/50 ,  G06F9/455

CPC分类号： G06F17/5081

摘要： A pattern forming method including modifying design data subjected to a first design rule check in design data of a pattern to be formed in a semiconductor substrate, performing the first design rule check to the modified design data again, outputting the modified design data which does not violate the first design rule as pattern forming design data used in actual pattern formation, and performing a second design rule check having an allowable range wider than that of the first design rule to the modified design data which violates the first design rule, and outputting the modified design data which does not violate the second design rule as the pattern forming design data, and redesigning the pattern to satisfy the second design rule or adjusting the modification guideline such that the modified design data which violates the second design rule satisfies the second design rule.

摘要翻译： 一种图案形成方法，包括修改经过第一设计规则的设计数据检查要在半导体衬底中形成的图案的设计数据，再次对经修改的设计数据执行第一设计规则检查，输出不改变的设计数据 违反第一设计规则作为在实际图案形成中使用的图案形成设计数据，并且对违反第一设计规则的修改后的设计数据执行具有比第一设计规则宽的容许范围的第二设计规则检查，并输出 修改的设计数据不违反第二设计规则作为图案形成设计数据，并且重新设计图案以满足第二设计规则或调整修改指南，使得违反第二设计规则的修改后的设计数据满足第二设计规则 。

公开(公告)号：US20110265047A1

公开(公告)日：2011-10-27

申请号：US13067810

申请日：2011-06-28

申请人： Sachiko Kobayashi ,  Toshiya Kotani ,  Shinichiroh Ohki ,  Hirotaka Ichikawa

发明人： Sachiko Kobayashi ,  Toshiya Kotani ,  Shinichiroh Ohki ,  Hirotaka Ichikawa

IPC分类号： G06F17/50

CPC分类号： G06F17/5068

摘要： Disclosed is a mask data processing method of correcting a hierarchical structure. In the case that in design data having a hierarchical structure including a plurality of cells each having a design pattern, when the total number of graphic forms or the total edge length of a design pattern on which the calculation of mask data processing is to be executed, the amount of calculation to be executed, or the expansion degree presumably becomes equal to or larger than a predetermined threshold value if the calculation of the mask data processing is executed on the design data having the initial hierarchical structure, the hierarchical structure is corrected. This correction is performed to reduce the total number of graphic forms or the total edge length of the design pattern on which the calculation is to be executed, the amount of calculation to be executed, of the expansion degree.

公开(公告)号：US20110177457A1

公开(公告)日：2011-07-21

申请号：US12984190

申请日：2011-01-04

申请人： Shimon MAEDA ,  Norikazu Ooishi ,  Sachiko Kobayashi

发明人： Shimon MAEDA ,  Norikazu Ooishi ,  Sachiko Kobayashi

IPC分类号： G03F7/20 ,  G06F17/50

CPC分类号： G03F1/36

摘要： According to the embodiment, a pattern after lithography is derived by using a mask pattern. The mask pattern is corrected by moving a first moving target pattern so that a first evaluation value calculated with respect to this pattern after lithography satisfies a first condition. Next, a pattern after lithography is derived by using the mask pattern after correction. The mask pattern after correction is further corrected by moving a second moving target pattern so that a second evaluation value calculated with respect to this pattern after lithography satisfies a second condition.

摘要翻译： 根据实施例，通过使用掩模图案导出光刻之后的图案。 通过移动第一移动目标图案来校正掩模图案，使得在光刻之后相对于该图案计算的第一评估值满足第一条件。 接下来，通过在校正后使用掩模图案导出光刻之后的图案。 校正后的掩模图案通过移动第二移动目标图案进一步校正，使得在光刻之后相对于该图案计算的第二评估值满足第二条件。

公开(公告)号：US07418694B2

公开(公告)日：2008-08-26

申请号：US11516783

申请日：2006-09-07

申请人： Sachiko Kobayashi ,  Atsuhiko Ikeuchi

发明人： Sachiko Kobayashi ,  Atsuhiko Ikeuchi

IPC分类号： G06F17/50 ,  G06F19/00 ,  G03F1/00 ,  G21K5/00

CPC分类号： H01L22/32 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for generating test patterns utilized in manufacturing a semiconductor device includes creating mini-data concerning a partial area pattern used in designing the semiconductor device, subjecting the mini-data to data processing in accordance with a condition of a manufacturing process of the semiconductor device, thereby creating processed mini-data, extracting a marginless point in the processed mini-data where a process margin is less than a predetermined threshold in a manufacturing process of the semiconductor device, determining a class of the marginless point in accordance with a criticality and a category of the marginless point, determining a parameter and a range of the parameter used for the marginless point in accordance with the class of the marginless point, and generating a plurality of test patterns to which different values of the parameter are respectively applied within the range.

摘要翻译： 一种用于产生用于制造半导体器件的测试图案的方法，包括：创建关于半导体器件设计中使用的部分区域图案的微型数据，根据半导体器件的制造过程的条件对微型数据进行数据处理 从而产生经处理的微型数据，在半导体器件的制造过程中提取处理裕度小于预定阈值的经处理的微型数据中的无边界点，根据临界性确定无边缘点的类别;以及 无边缘点的类别，根据无边缘点的类别确定用于无边缘点的参数的参数和范围，以及生成多个测试图案，在该测试图案中分别应用参数的不同值 范围。