公开(公告)号：US20110265047A1

公开(公告)日：2011-10-27

申请号：US13067810

申请日：2011-06-28

Applicant: Sachiko Kobayashi ,  Toshiya Kotani ,  Shinichiroh Ohki ,  Hirotaka Ichikawa

Inventor： Sachiko Kobayashi ,  Toshiya Kotani ,  Shinichiroh Ohki ,  Hirotaka Ichikawa

IPC: G06F17/50

CPC classification number: G06F17/5068

Abstract: Disclosed is a mask data processing method of correcting a hierarchical structure. In the case that in design data having a hierarchical structure including a plurality of cells each having a design pattern, when the total number of graphic forms or the total edge length of a design pattern on which the calculation of mask data processing is to be executed, the amount of calculation to be executed, or the expansion degree presumably becomes equal to or larger than a predetermined threshold value if the calculation of the mask data processing is executed on the design data having the initial hierarchical structure, the hierarchical structure is corrected. This correction is performed to reduce the total number of graphic forms or the total edge length of the design pattern on which the calculation is to be executed, the amount of calculation to be executed, of the expansion degree.

公开(公告)号：US06907596B2

公开(公告)日：2005-06-14

申请号：US10385624

申请日：2003-03-12

Applicant: Sachiko Kobayashi ,  Toshiya Kotani ,  Satoshi Tanaka ,  Susumu Watanabe

Inventor： Sachiko Kobayashi ,  Toshiya Kotani ,  Satoshi Tanaka ,  Susumu Watanabe

IPC: G03F1/36 ,  G03F1/68 ,  G03F1/70 ,  H01L21/027 ,  H01L21/82 ,  G06F17/50

CPC classification number: G03F1/36

Abstract: A mask data generating apparatus comprising: a division module configured to extract a line segment and dividing the extracted line segment into a suitable length; a correction value calculation module configured to calculate correction value calculating points from each divided edge; a first calculated center point calculation module configured to set first calculated center points and a shape of a pattern; a first rectangular region preparation module configured to prepare first simulation regions and a plurality of first rectangular regions which overlap with each other; a second calculated center point calculation module configured to acquire second rectangular regions, and calculating second calculated center points based on the second rectangular regions; a second simulation region preparation module configured to acquire second simulation regions; a process simulation execution module configured to calculate a correction value; and a correction pattern preparation module configured to prepare the correction pattern.

Abstract translation: 一种掩模数据生成装置，包括：分割模块，被配置为提取线段并将所提取的线段划分成合适的长度; 校正值计算模块，被配置为从每个分割边缘计算校正值计算点; 第一计算中心点计算模块，被配置为设置第一计算的中心点和图案的形状; 第一矩形区域准备模块，被配置为准备第一模拟区域和彼此重叠的多个第一矩形区域; 第二计算中心点计算模块，被配置为获取第二矩形区域，并且基于所述第二矩形区域计算第二计算的中心点; 配置成获取第二模拟区域的第二模拟区域准备模块; 被配置为计算校正值的过程模拟执行模块; 以及配置为准备校正图案的校正图案准备模块。

公开(公告)号：US20070124718A1

公开(公告)日：2007-05-31

申请号：US11440086

申请日：2006-05-25

Applicant: Sachiko Kobayashi ,  Toshiya Kotani

Inventor： Sachiko Kobayashi ,  Toshiya Kotani

IPC: G06F17/50

CPC classification number: G03F1/68 ,  G03F1/36

Abstract: A mask manufacturing system and a mask data creating method reusing data for processing information and environment in the past to reduce a photomask developing period, and a manufacturing method of a semiconductor device are disclosed. According to one aspect of the present invention, it is provided a mask manufacturing system comprising a storage device storing processing data for semiconductor integrated circuits processed in the past, a plurality of operation processing modules, a module selecting section selecting at least one operation processing modules, an optical proximity effect correction section executing optical proximity effect correction to a processing object data and generating a correction data by utilizing past correction information applied for a stored data equivalent to the processing object data, a converting section converting the processing object data into mask data, and a drawing system drawing a mask pattern based on the mask data.

Abstract translation: 掩模制造系统和掩模数据创建方法重复利用用于处理信息和环境的数据以减少光掩模生长期，以及半导体器件的制造方法。 根据本发明的一个方面，提供了一种掩模制造系统，包括存储用于过去处理的半导体集成电路的处理数据的存储装置，多个操作处理模块，模块选择部分，其选择至少一个操作处理模块 光学接近效应校正部分，对处理对象数据执行光学邻近效应校正，并通过利用应用于与处理对象数据相当的存储数据的过去校正信息产生校正数据;转换部分，将处理对象数据转换成掩模数据 以及基于掩模数据绘制掩模图案的绘图系统。

公开(公告)号：US08443310B2

公开(公告)日：2013-05-14

申请号：US13237435

申请日：2011-09-20

Applicant: Masanari Kajiwara ,  Toshiya Kotani ,  Sachiko Kobayashi ,  Hiromitsu Mashita ,  Fumiharu Nakajima

Inventor： Masanari Kajiwara ,  Toshiya Kotani ,  Sachiko Kobayashi ,  Hiromitsu Mashita ,  Fumiharu Nakajima

IPC: G06F17/50

CPC classification number: G03F1/36 ,  G03F1/70 ,  G03F7/70441

Abstract: A pattern correcting method of an embodiment computes a distribution of pattern coverages on a design layout of a circuit pattern in the vicinity of a position that becomes an error pattern in a case where an on-substrate pattern is formed. Then, an area on the design layout in which a difference in the distribution of the pattern coverages becomes small by adding an addition pattern is set as an addition area. Next, addition pattern candidates to be added to the addition area are generated, an addition pattern to be added to the design layout is selected from the candidates on the basis of a predetermined selection criterion, and the addition pattern is added to the addition area.

Abstract translation: 实施例的图案校正方法在形成有衬底图案的情况下，在成为误差图案的位置附近的电路图案的设计布局上计算图案覆盖率的分布。 然后，通过添加加法图案，设置图案覆盖物的分布差异变小的设计布局上的区域作为附加区域。 接下来，生成要添加到相加区域的添加模式候选，并根据预定的选择标准从候选中选择要添加到设计布局的添加模式，并将添加模式添加到添加区域。

公开(公告)号：US07530049B2

公开(公告)日：2009-05-05

申请号：US11440086

申请日：2006-05-25

Applicant: Sachiko Kobayashi ,  Toshiya Kotani

Inventor： Sachiko Kobayashi ,  Toshiya Kotani

IPC: G06F17/50

CPC classification number: G03F1/68 ,  G03F1/36

Abstract: A mask manufacturing system and a mask data creating method reusing data for processing information and environment in the past to reduce a photomask developing period, and a manufacturing method of a semiconductor device are disclosed. According to one aspect of the present invention, it is provided a mask manufacturing system comprising a storage device storing processing data for semiconductor integrated circuits processed in the past, a plurality of operation processing modules, a module selecting section selecting at least one operation processing modules, an optical proximity effect correction section executing optical proximity effect correction to a processing object data and generating a correction data by utilizing past correction information applied for a stored data equivalent to the processing object data, a converting section converting the processing object data into mask data, and a drawing system drawing a mask pattern based on the mask data.

Abstract translation: 掩模制造系统和掩模数据创建方法重复利用用于处理信息和环境的数据以减少光掩模生长期，以及半导体器件的制造方法。 根据本发明的一个方面，提供了一种掩模制造系统，包括存储用于过去处理的半导体集成电路的处理数据的存储装置，多个操作处理模块，模块选择部分，其选择至少一个操作处理模块 光学接近效应校正部分，对处理对象数据执行光学邻近效应校正，并通过利用应用于与处理对象数据相当的存储数据的过去校正信息产生校正数据;转换部分，将处理对象数据转换成掩模数据 以及基于掩模数据绘制掩模图案的绘图系统。

公开(公告)号：US07065739B2

公开(公告)日：2006-06-20

申请号：US10331005

申请日：2002-12-27

Applicant: Sachiko Kobayashi ,  Toshiya Kotani ,  Satoshi Tanaka ,  Susumu Watanabe ,  Mitsuhiro Yano

Inventor： Sachiko Kobayashi ,  Toshiya Kotani ,  Satoshi Tanaka ,  Susumu Watanabe ,  Mitsuhiro Yano

IPC: G06F17/50 ,  G03F1/00

CPC classification number: G03F1/36 ,  G03F7/70441

Abstract: A pattern correction method executed by a computer includes a first correction and a second correction. The first correction is executed by calculating a correction value, in consideration for an optical proximity effect, for edges (first edges) meeting a condition among the edges constituting a designed pattern. Subsequently, The second correction is executed for an edge (second edge) which does not meet the condition, by use of the correction value of any one of the edges (first edges) adjacent to the second edge among the first edges for which the first correction is executed, thus connecting the corrected first edge and the corrected second edge by a line segment. The pattern is corrected to a shape suitable for a mask drawing and a check with simple processing.

Abstract translation: 由计算机执行的图案校正方法包括第一校正和第二校正。 对于构成设计图案的边缘中满足条件的边缘（第一边缘），考虑光学邻近效应来计算校正值来执行第一校正。 随后，对于不符合条件的边缘（第二边缘），通过使用与第一边缘相邻的边缘（第一边缘）中的任何一个边缘（第一边缘）的第一边缘的第一边缘 执行校正，从而将校正的第一边缘和校正的第二边缘连接到线段。 该图案被校正为适于掩模绘图和具有简单处理的检查的形状。

公开(公告)号：US06964031B2

公开(公告)日：2005-11-08

申请号：US10255832

申请日：2002-09-27

Applicant: Toshiya Kotani ,  Satoshi Tanaka ,  Soichi Inoue ,  Sachiko Kobayashi ,  Hirotaka Ichiakwa

Inventor： Toshiya Kotani ,  Satoshi Tanaka ,  Soichi Inoue ,  Sachiko Kobayashi ,  Hirotaka Ichiakwa

IPC: H01L21/027 ,  G03F1/00 ,  G03F1/36 ,  G06F17/50 ,  H01L21/00

CPC classification number: G03F1/36

Abstract: A mask pattern generation method of generating a mask pattern from a designed pattern, comprising preparing the designed pattern, preparing a correction parameter, preparing a first correction library in which a plurality of pairs of an edge coordinate group and a correction value group to correct the edge coordinate group is registered, acquiring edge coordinate groups of the designed patterns, generating a second correction library in which only the plurality of pairs of an edge coordinate group agreeing with the acquired edge coordinate group and the correction value group is registered in the first correction library and simulation using the correction parameter, and correcting the designed pattern using the second correction library.

Abstract translation: 一种从设计图案生成掩模图案的掩模图案生成方法，包括准备设计图案，准备校正参数，准备第一校正库，其中多对边缘坐标组和校正值组校正第 登记边缘坐标组，获取所设计图案的边缘坐标组，生成第二校正库，其中在所述第一校正中仅登记与获取的边缘坐标组和校正值组一致的边缘坐标组的多对对 库和模拟，并使用第二校正库校正设计的模式。

公开(公告)号：US07996794B2

公开(公告)日：2011-08-09

申请号：US11945697

申请日：2007-11-27

Applicant: Sachiko Kobayashi ,  Toshiya Kotani ,  Shinichiroh Ohki ,  Hirotaka Ichikawa

Inventor： Sachiko Kobayashi ,  Toshiya Kotani ,  Shinichiroh Ohki ,  Hirotaka Ichikawa

IPC: G06F17/50

CPC classification number: G06F17/5068

Abstract: Disclosed is a mask data processing method of correcting a hierarchical structure. In the case that in design data having a hierarchical structure including a plurality of cells each having a design pattern, when the total number of graphic forms or the total edge length of a design pattern on which the calculation of mask data processing is to be executed, the amount of calculation to be executed, or the expansion degree presumably becomes equal to or larger than a predetermined threshold value if the calculation of the mask data processing is executed on the design data having the initial hierarchical structure, the hierarchical structure is corrected. This correction is performed to reduce the total number of graphic forms or the total edge length of the design pattern on which the calculation is to be executed, the amount of calculation to be executed, of the expansion degree.

Abstract translation: 公开了一种校正层次结构的掩模数据处理方法。 在具有包括多个单元的设计数据的设计数据中，每个单元均具有设计图案时，当要执行掩模数据处理的计算的设计图案的总数或总边沿长度时 如果对具有初始层次结构的设计数据执行掩模数据处理的计算，则修正了要执行的计算量或扩展度等于或大于预定阈值等于或大于预定阈值。 执行该校正以减少要执行计算的设计模式的总数或总边缘长度，即要执行的计算量，扩展度。

公开(公告)号：US20120198396A1

公开(公告)日：2012-08-02

申请号：US13237854

申请日：2011-09-20

Applicant: Masanari KAJIWARA ,  Sachiko Kobayashi ,  Satoshi Tanaka ,  Kazuhiro Takahata ,  Shigeki Nojima ,  Toshiya Kotani ,  Shimon Maeda

Inventor： Masanari KAJIWARA ,  Sachiko Kobayashi ,  Satoshi Tanaka ,  Kazuhiro Takahata ,  Shigeki Nojima ,  Toshiya Kotani ,  Shimon Maeda

IPC: G06F17/50

CPC classification number: H01L22/20 ,  H01L22/12 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of optimizing a semiconductor device manufacturing process according to an embodiment is a method of optimizing a semiconductor device manufacturing process in which a pattern based on circuit design is formed. The method of optimizing a semiconductor device manufacturing process according to the embodiment includes: at the time of calculation of a statistic amount based on a distribution of differences at a plurality of sites between a pattern formed by a first exposing apparatus in a first condition and a pattern formed by a second exposing apparatus in a second condition, calculating the statistic amount after applying weighting to the differences based on information on an electrical characteristic; and repeating the calculating with the second condition being changed, and selecting an condition in which the total sum becomes a minimum or equal to or less than a standard value as an optimized condition of the second exposing apparatus.

Abstract translation: 根据实施例的优化半导体器件制造工艺的方法是优化其中形成基于电路设计的图案的半导体器件制造工艺的方法。 根据实施例的半导体器件制造方法的优化方法包括：在基于在第一状态下由第一曝光装置形成的图案与第一状态之间的多个位置处的差异的分布的统计量的计算时， 在第二状态下由第二曝光装置形成的图案，基于关于电特性的信息对所述差进行加权计算后的统计量; 并重复进行第二条件的计算，并且选择总和变为最小或等于或小于标准值的条件作为第二曝光装置的优化条件。

公开(公告)号：US20080216045A1

公开(公告)日：2008-09-04

申请号：US11945697

申请日：2007-11-27

Applicant: Sachiko KOBAYASHI ,  Toshiya Kotani ,  Shinichiroh Ohki ,  Hirotaka Ichikawa

Inventor： Sachiko KOBAYASHI ,  Toshiya Kotani ,  Shinichiroh Ohki ,  Hirotaka Ichikawa

IPC: G06F17/50

CPC classification number: G06F17/5068

Abstract: Disclosed is a mask data processing method of correcting a hierarchical structure. In the case that in design data having a hierarchical structure including a plurality of cells each having a design pattern, when the total number of graphic forms or the total edge length of a design pattern on which the calculation of mask data processing is to be executed, the amount of calculation to be executed, or the expansion degree presumably becomes equal to or larger than a predetermined threshold value if the calculation of the mask data processing is executed on the design data having the initial hierarchical structure, the hierarchical structure is corrected. This correction is performed to reduce the total number of graphic forms or the total edge length of the design pattern on which the calculation is to be executed, the amount of calculation to be executed, of the expansion degree.

Abstract translation: 公开了一种校正层次结构的掩模数据处理方法。 在具有包括多个单元的设计数据的设计数据中，每个单元均具有设计图案时，当要执行掩模数据处理的计算的设计图案的总数或总边缘长度时 如果对具有初始层次结构的设计数据执行掩模数据处理的计算，则修正了要执行的计算量或扩展度等于或大于预定阈值等于或大于预定阈值。 执行该校正以减少要执行计算的设计模式的总数或总边缘长度，即要执行的计算量，扩展度。