Low loss interconnect structure for use in microelectronic circuits
    31.
    发明授权
    Low loss interconnect structure for use in microelectronic circuits 有权
    用于微电子电路的低损耗互连结构

    公开(公告)号:US07352059B2

    公开(公告)日:2008-04-01

    申请号:US11152643

    申请日:2005-06-14

    摘要: A low loss on-die interconnect structure includes first and second differential signal lines on one of the metal layers of a microelectronic die. One or more traces may also be provided on another metal layer of the die that are non-parallel (e.g., orthogonal) to the differential signal lines. Because the traces are non-parallel, they provide a relatively high impedance return path for signals on the differential signal lines. Thus, a signal return path through the opposite differential line predominates for the signals on the differential lines. In one application, the low loss interconnect structure is used within an on-die salphasic clock distribution network.

    摘要翻译: 低损耗管芯互连结构包括在微电子管芯的金属层之一上的第一和第二差分信号线。 还可以在与差分信号线不平行(例如,正交))的管芯的另一金属层上提供一个或多个迹线。 由于迹线不平行,它们为差分信号线上的信号提供了相对较高的阻抗返回路径。 因此,通过相反的微分线路的信号返回路径对于差分线路上的信号占优势。 在一个应用中,低损耗互连结构用于管芯内的相关时钟分配网络。

    Reference impedance apparatus, systems, and methods
    32.
    发明授权
    Reference impedance apparatus, systems, and methods 有权
    参考阻抗装置,系统和方法

    公开(公告)号:US06998931B2

    公开(公告)日:2006-02-14

    申请号:US10336233

    申请日:2003-01-03

    IPC分类号: H03H7/38

    CPC分类号: H03H7/38

    摘要: An apparatus and system may include a microstrip line capable of being coupled to an amplifier, wherein the microstrip line is to transform an input impedance of the amplifier to a substantially resistive value, and wherein the microstrip line has a characteristic impedance approximately equal to a selected system reference impedance. The apparatus and system may include a transformer coupled to the microstrip line, wherein the transformer is to transform the substantially resistive value into approximately a resistance of a source impedance included in a source. An article may include data, which, when accessed, results in a machine performing a method including simulating selecting a system having a reference impedance and simulating coupling an amplifier having an input impedance to a source having a source impedance using a transformer coupled to a microstrip line.

    摘要翻译: 装置和系统可以包括能够耦合到放大器的微带线,其中微带线将放大器的输入阻抗转换成基本上电阻的值,并且其中微带线具有大约等于所选择的特性阻抗的特性阻抗 系统参考阻抗。 该装置和系统可以包括耦合到微带线的变压器,其中变压器将基本上电阻值转换成源中包括的源阻抗的大致电阻。 物品可以包括数据,当被访问时,这导致机器执行包括模拟选择具有参考阻抗的系统的方法的机器,并且使用耦合到微带的变压器来模拟将具有输入阻抗的放大器耦合到具有源阻抗的源 线。

    Device and method of quadrature oscillation
    33.
    发明授权
    Device and method of quadrature oscillation 有权
    正交振荡的装置和方法

    公开(公告)号:US06937107B2

    公开(公告)日:2005-08-30

    申请号:US10608549

    申请日:2003-06-30

    IPC分类号: H03B5/12 H03B27/00 H03B25/00

    摘要: Briefly, devices and methods for tuning of quadrature oscillators which may be used, for example, in a Complementary Metal-Oxide Semiconductor (CMOS) process. Devices and methods in accordance with some exemplary embodiments of the invention may allow, for example, improved locking, tuning and performance of slave oscillators and a master oscillator within a quadrature oscillator utilizing injection-locking.

    摘要翻译: 简单地说,可用于例如在互补金属氧化物半导体(CMOS)工艺中使用的正交振荡器的调谐的装置和方法。 根据本发明的一些示例性实施例的装置和方法可以允许例如利用注射锁定的正交振荡器中的从属振荡器和主振荡器的锁定,调谐和性能的改进。

    Fast dual-rail dynamic logic style
    36.
    发明授权
    Fast dual-rail dynamic logic style 失效
    快速双轨动态逻辑风格

    公开(公告)号:US06838910B2

    公开(公告)日:2005-01-04

    申请号:US10633127

    申请日:2003-08-01

    IPC分类号: H03K3/356 H03K19/096

    CPC分类号: H03K3/356113 H03K3/356173

    摘要: A dual-rail static logic gate with a self cut-off mechanism is disclosed. In an embodiment, the output of the first rail is coupled to the input of the pull-up device of the second rail and vice versa. The cross-coupling allows the self cut-off mechanism of the static gate to function properly and provides for components which have lower capacitance than conventional static gates. The lower capacitance results in a faster static gate.

    摘要翻译: 公开了一种具有自动切断机构的双轨静态逻辑门。 在一个实施例中,第一轨道的输出耦合到第二轨道的上拉装置的输入端,反之亦然。 交叉耦合允许静态门的自我截止机制正常工作,并提供具有比常规静态门更低的电容的组件。 较低的电容导致更快的静态栅极。

    Flash [II]-Domino: a fast dual-rail dynamic logic style
    37.
    发明授权
    Flash [II]-Domino: a fast dual-rail dynamic logic style 失效
    Flash [II] -Domino:快速双轨动态逻辑风格

    公开(公告)号:US06717441B2

    公开(公告)日:2004-04-06

    申请号:US10021544

    申请日:2001-10-22

    IPC分类号: H03K19096

    CPC分类号: H03K3/356113 H03K3/356173

    摘要: A dual-rail static logic gate with a self cut-off mechanism is disclosed. In an embodiment, the output of the first rail is coupled to the input of the pull-up device of the second rail and vice versa. The cross-coupling allows the self cut-off mechanism of the static gate to function properly and provides for components which have lower capacitance than conventional static gates. The lower capacitance results in a faster static gate.

    摘要翻译: 公开了一种具有自动切断机构的双轨静态逻辑门。 在一个实施例中,第一轨道的输出耦合到第二轨道的上拉装置的输入端,反之亦然。 交叉耦合允许静态门的自我截止机制正常工作,并提供具有比常规静态门更低的电容的组件。 较低的电容导致更快的静态栅极。

    Area efficient waveform evaluation and DC offset cancellation circuits
    38.
    发明授权
    Area efficient waveform evaluation and DC offset cancellation circuits 失效
    区域效率波形评估和直流偏移消除电路

    公开(公告)号:US06714054B2

    公开(公告)日:2004-03-30

    申请号:US10118816

    申请日:2002-04-08

    IPC分类号: H03K1700

    摘要: Analog circuits for providing one or more waveform parameters, e.g., the DC offset or average, of an analog input signal. Separate biasing is not necessarily required. Some embodiments comprise field-effect-transistors (FETs) configured in various diode-connected configurations that take advantage of leakage currents through the FETs so that long resistors or large capacitors are not necessarily required. One embodiment comprises two diode-connected FETs to provide an unbiased DC offset voltage of an analog input signal.

    摘要翻译: 用于提供模拟输入信号的一个或多个波形参数(例如,DC偏移或平均)的模拟电路。 不一定需要单独的偏置。 一些实施例包括配置在各种二极管连接配置中的场效应晶体管(FET),其利用通过FET的漏电流,使得不一定需要长电阻器或大电容器。 一个实施例包括两个二极管连接的FET,以提供模拟输入信号的无偏置DC偏移电压。

    Low voltage PVT insensitive MOSFET based voltage reference circuit
    39.
    发明授权
    Low voltage PVT insensitive MOSFET based voltage reference circuit 失效
    低压PVT不敏感MOSFET基电压基准电路

    公开(公告)号:US06518833B2

    公开(公告)日:2003-02-11

    申请号:US09470275

    申请日:1999-12-22

    IPC分类号: G05F110

    CPC分类号: G05F3/242 G05F3/262

    摘要: Methods and apparatus for generating a MOSFET based voltage reference circuit with automatic trimming of resistors to compensate for process and supply voltage variations and to improve the accuracy of a MOSFET based reference voltage circuit, a temperature compensated MOSFET based reference voltage, and arbitrary translation of the MOSFET based reference voltage with or without trimming are provided.

    摘要翻译: 用于产生基于MOSFET的电压参考电路的方法和装置,其具有自动微调电阻器以补偿过程和电源电压变化并提高基于MOSFET的参考电压电路的精度,基于温度补偿的MOSFET的参考电压和任意的 提供了具有或不具有微调功能的基于MOSFET的参考电压。

    Digital transmitter and methods of generating radio-frequency signals using time-domain outphasing
    40.
    发明授权
    Digital transmitter and methods of generating radio-frequency signals using time-domain outphasing 有权
    数字发射机和使用时域外相生成射频信号的方法

    公开(公告)号:US07715493B2

    公开(公告)日:2010-05-11

    申请号:US11464352

    申请日:2006-08-14

    IPC分类号: H04L25/49 H04B1/04

    摘要: Embodiments of a multicarrier transmitter and method of generating an RF signal for transmission are generally described herein. Other embodiments may be described and claimed. In some embodiments, a multicarrier transmitter generates RF signals for transmission using non-linear switching power amplifiers to amplify outphased switching waveforms allowing the multicarrier transmitter to operate more efficiently than some conventional multicarrier transmitters.

    摘要翻译: 多载波发射器的实施例和用于产生用于传输的RF信号的方法在本文中大体上被描述。 可以描述和要求保护其他实施例。 在一些实施例中,多载波发射机使用非线性开关功率放大器生成用于传输的RF信号,以放大允许多载波发射机比一些常规多载波发射机更有效地操作的外切开关波形。