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121 条记录 (耗时 0.036 秒)

    Wire electric discharge machine
    31.
    发明授权
    Wire electric discharge machine 有权
    线放电机

    公开(公告)号：US06998561B2

    公开(公告)日：2006-02-14

    申请号：US10689634

    申请日：2003-10-22

    申请人： Junichi Kato ,  Keiichiro Miyajima ,  Yasuo Arakawa ,  Toshiyuki Ogata

    发明人： Junichi Kato ,  Keiichiro Miyajima ,  Yasuo Arakawa ,  Toshiyuki Ogata

    IPC分类号： B23H7/06

    CPC分类号： B23H7/065 ,  B23H2500/20

    摘要： A wire electric discharge machine capable of preventing a straightness error from being caused by consumption of a wire electrode, to eliminate insufficient machining. A correction angle φ is predetermined for preventing the straightness error of the workpiece due to consumption. Correction amounts d1′, d2′ on a program plane and an upper surface of a workpiece, respectively, are determined based on the predetermined correction angle φ, and are added to or substracted from a predetermined offset amount depending on a wire electrode radius and an electric discharging gap, to determine corrected offset amounts d1, d2 on the program plane and the upper surface of the workpiece, respectively. Correction amounts dlo, dup for lower and upper wire guides in an offset direction are obtained based on the corrected offset amounts d1, d2, respectively, so that motion paths of upper and lower wire guides relative to the workpiece are determined.

    摘要翻译： 一种能够防止线电极消耗引起的平直度误差的电线放电机，消除不充分的加工。 为了防止由于消耗引起的工件的直线度误差，修正角度φi是预定的。 基于预定的校正角度phi来确定编程平面和工件的上表面上的校正量d 1'，d 2'，并且根据线电极半径 和放电间隙，以分别确定编程平面和工件的上表面上的校正偏移量d 1，d 2。 基于校正的偏移量d 1，d 2分别获得偏移方向上下导线器的修正量dlo，dup，从而确定上，下导线器相对于工件的运动路径。

    Non-volatile semiconductor memory device
    32.
    发明申请
    Non-volatile semiconductor memory device 有权
    非易失性半导体存储器件

    公开(公告)号：US20050276103A1

    公开(公告)日：2005-12-15

    申请号：US11143581

    申请日：2005-06-03

    申请人： Junichi Kato ,  Masayoshi Nakayama ,  Takao Ozeki ,  Asako Miyoshi ,  Shinichi Hatakeyama

    发明人： Junichi Kato ,  Masayoshi Nakayama ,  Takao Ozeki ,  Asako Miyoshi ,  Shinichi Hatakeyama

    IPC分类号： G11C11/34 ,  G11C14/00 ,  G11C16/04

    CPC分类号： G11C14/00 ,  G11C16/0441

    摘要： A switch section connects a first wire line aSL to the gate of a first memory transistor 1 and the source of a second memory transistor 2 and a second wire line bSL to the source of the first memory transistor 1 and the gate of the second memory transistor 2 when first type data is to be written into a memory cell; and connects the first wire line aSL to the source of the first memory transistor 1 and the gate of the second memory transistor 2 and the second wire line bSL to the gate of the first memory transistor 1 and the source of the second memory transistor 2 when second type data is to be written into a memory cell.

    摘要翻译： 开关部分将第一有线线路aSL连接到第一存储晶体管1的栅极和第二存储晶体管2的源极和第二有线线路bSL连接到第一存储晶体管1的源极和第二存储晶体管的栅极 当第一类数据被写入存储单元时; 并且将第一有线线路aSL连接到第一存储晶体管1的源极和第二存储晶体管2的栅极和第二有线线路bSL到第一存储晶体管1的栅极和第二存储晶体管2的源极， 第二类型数据将被写入存储单元。

    Dielectric ceramic composition and dielectric device
    34.
    发明授权
    Dielectric ceramic composition and dielectric device 失效
    介电陶瓷组合物和电介质器件

    公开(公告)号：US06835681B2

    公开(公告)日：2004-12-28

    申请号：US10027620

    申请日：2001-12-19

    申请人： Kojiro Okuyama ,  Hiroshi Kagata ,  Junichi Kato ,  Hiroyuki Hase

    发明人： Kojiro Okuyama ,  Hiroshi Kagata ,  Junichi Kato ,  Hiroyuki Hase

    IPC分类号： C03C1400

    CPC分类号： H01P1/20345 ,  C03C8/18 ,  C03C8/20 ,  C03C14/004 ,  C04B35/49 ,  H01G4/1245 ,  H01G4/1263 ,  H01G4/129

    摘要： A dielectric ceramic composition containing a first component and a second component (25 to 80 wt %) is used. The first component is a complex oxide represented by Formula: xZrO2-yTiO2-zL(1+u)/3M(2−u)/3O2 (L is at least one element selected from the group consisting of Mg, Zn, Co, and Mn, and M is at least one element selected from the group consisting of Nb and Tb. x, y, z, and u are numerical values represented by x+y+z=1, 0.10≦x≦0.60, 0.20 ≦y≦0.60, 0.01≦z≦0.70, 0≦u≦1.90). The second component is a glass composition containing an oxide of at least one element selected from the group consisting of Si, B, Al, Ba, Ca, Sr, Zn, Ti, La, and Nd.

    摘要翻译： 使用含有第一成分和第二成分（25〜80重量％）的电介质陶瓷组合物。 第一组分是由下式表示的复合氧化物：xZrO2-yTiO2-zL（1 + u）/ 3M（2-u）/ 3O2（L是选自Mg，Zn，Co和 Mn和M是选自Nb和Tb中的至少一种元素，x，y，z，u是由x + y + z = 1，0.10 <= x <= 0.60,0.20， = y <= 0.60,0.01 <= z <= 0.70,0 <= u <= 1.90）。 第二组分是含有选自Si，B，Al，Ba，Ca，Sr，Zn，Ti，La和Nd中的至少一种元素的氧化物的玻璃组合物。

    Device for deterring cable displacement
    35.
    发明授权
    Device for deterring cable displacement 失效
    用于阻止电缆位移的装置

    公开(公告)号：US06706965B2

    公开(公告)日：2004-03-16

    申请号：US10078312

    申请日：2002-02-15

    申请人： Junichi Kato ,  Renato Ravanello

    发明人： Junichi Kato ,  Renato Ravanello

    IPC分类号： H01B734

    CPC分类号： H01R4/726 ,  H01R13/5216

    摘要： A device for deterring displacement of a cable is effectuated in an embodiment of the invention by an enclosure that envelopes the cable and an affixing mechanism that couples the enclosure to the cable, where the cable is oriented in an assembly such that the enclosure contacts a feature internal to the assembly and deters displacement of the cable.

    摘要翻译： 用于阻止电缆的位移的装置在本发明的实施例中通过包围电缆的外壳和将外壳耦合到电缆的固定机构来实现，其中电缆被定位在组件中，使得外壳接触特征 在组件内部并阻止电缆的位移。

    Nonvolatile semiconductor device capable of increased electron injection efficiency
    36.
    发明授权
    Nonvolatile semiconductor device capable of increased electron injection efficiency 失效
    能够提高电子注入效率的非易失性半导体器件

    公开(公告)号：US06380585B1

    公开(公告)日：2002-04-30

    申请号：US09588308

    申请日：2000-06-06

    申请人： Shinji Odanaka ,  Kaori Akamatsu ,  Junichi Kato ,  Atsushi Hori ,  Seiki Ogura

    发明人： Shinji Odanaka ,  Kaori Akamatsu ,  Junichi Kato ,  Atsushi Hori ,  Seiki Ogura

    IPC分类号： H01L29788

    CPC分类号： H01L29/66825 ,  H01L29/42324 ,  H01L29/7885

    摘要： The nonvolatile semiconductor memory device of the present invention includes: a semiconductor substrate having a surface including a first surface region at a first level, a second surface region at a second level lower than the first level, and a step side region linking the first surface region and the second surface region together; a channel region formed in the first surface region of the semiconductor substrate; a source region and a drain region which are formed in the surface of the semiconductor substrate so as to interpose the channel region therebetween; a first insulating film formed on the surface of the semiconductor substrate; a floating gate formed on the first insulating film; a second insulating film formed on the floating gate; and a control gate which is capacitively coupled to the floating gate via the second insulating film. The drain region includes a low-concentration impurity layer which is formed in the second surface region and which has one end extending toward the step side region, and a high-concentration impurity layer which is connected to the low-concentration impurity layer and which is formed in a region distant from the channel region. As impurity concentration of the low-concentration impurity layer is lower than an impurity concentration of the high-concentration impurity layer. The floating gate covers the step side region and at least a part of the low-concentration impurity layer via the first insulating film.

    摘要翻译： 本发明的非易失性半导体存储器件包括：半导体衬底，具有包括第一层的第一表面区域，低于第一层次的第二层的第二表面区域和将第一表面 区域和第二表面区域在一起; 形成在所述半导体衬底的所述第一表面区域中的沟道区; 源极区域和漏极区域，其形成在半导体衬底的表面中，以便在其间插入沟道区域; 形成在所述半导体衬底的表面上的第一绝缘膜; 形成在第一绝缘膜上的浮栅; 形成在浮动栅极上的第二绝缘膜; 以及通过第二绝缘膜电容耦合到浮动栅极的控制栅极。 漏区包括形成在第二表面区域中并且具有朝向台阶侧区域延伸的一端的低浓度杂质层和连接到低浓度杂质层的高浓度杂质层， 形成在远离通道区域的区域中。 由于低浓度杂质层的杂质浓度低于高浓度杂质层的杂质浓度。 浮置栅极经由第一绝缘膜覆盖台阶侧区域和至少一部分低浓度杂质层。

    Nonvolatile semiconductor memory device and method for fabricating the same, and semiconductor integrated circuit device
    37.
    发明授权
    Nonvolatile semiconductor memory device and method for fabricating the same, and semiconductor integrated circuit device 失效
    非易失性半导体存储器件及其制造方法以及半导体集成电路器件

    公开(公告)号：US06358799B2

    公开(公告)日：2002-03-19

    申请号：US09727536

    申请日：2000-12-04

    申请人： Shinji Odanaka ,  Kaori Akamatsu ,  Junichi Kato ,  Atsushi Hori ,  Seiki Ogura

    发明人： Shinji Odanaka ,  Kaori Akamatsu ,  Junichi Kato ,  Atsushi Hori ,  Seiki Ogura

    IPC分类号： H01L21336

    CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/7885

    摘要： In a semiconductor substrate having a surface including a first surface region at a first level, a second surface region at a second level lower than the first level, and a step side region linking the first surface region and the second surface region together, a channel region has a triple structure. Thus, a high electric field is formed in a corner portion between the step side region and the second surface region and in the vicinity thereof. A high electric field is also formed in the first surface region. As a result, the efficiency, with which electrons are injected into a floating gate, is considerably increased.

    摘要翻译： 在具有包括第一水平的第一表面区域的表面的半导体衬底中，具有低于第一水平的第二水平的第二表面区域和将第一表面区域和第二表面区域连接在一起的阶梯侧区域，通道 区域有三重结构。 因此，在台阶侧区域和第二表面区域之间的角部及其附近形成高电场。 在第一表面区域也形成高电场。 结果，电子注入浮栅的效率大大增加。

    Charging member, process cartridge, and image forming apparatus
    38.
    发明授权
    Charging member, process cartridge, and image forming apparatus 失效
    充电部件，处理盒和成像设备

    公开(公告)号：US06317574B1

    公开(公告)日：2001-11-13

    申请号：US09510341

    申请日：2000-02-22

    申请人： Seiichi Shinohara ,  Junichi Kato ,  Satoru Inami ,  Atsutoshi Ando ,  Yusuke Nakazono

    发明人： Seiichi Shinohara ,  Junichi Kato ,  Satoru Inami ,  Atsutoshi Ando ,  Yusuke Nakazono

    IPC分类号： G03G1502

    CPC分类号： G03G15/0233

    摘要： A charging member is disposed in contact with an electrophotographic photosensitive member and charges the surface of the electrophotographic photosensitive member electrostatically upon application of a voltage. The charging member has a conductive support, a base layer and a surface layer which are formed on the conductive support. The surface layer contains fluorine resin particles as a filler and a fluorine resin as a binder resin.

    摘要翻译： 充电构件设置成与电子照相感光构件接触，并且在施加电压时静电地对静电感光构件的表面充电。 充电构件具有形成在导电支撑件上的导电支撑件，基底层和表面层。 表面层含有作为填料的氟树脂颗粒和作为粘合剂树脂的氟树脂。

    Method for manufacturing a nonvolatile semiconductor memory device having increased hot electron injection efficiency
    39.
    发明授权
    Method for manufacturing a nonvolatile semiconductor memory device having increased hot electron injection efficiency 失效
    制造具有增加的热电子注入效率的非易失性半导体存储器件的方法

    公开(公告)号：US06303438B1

    公开(公告)日：2001-10-16

    申请号：US09017216

    申请日：1998-02-02

    申请人： Atsushi Hori ,  Junichi Kato ,  Shinji Odanaka ,  Seiki Ogura

    发明人： Atsushi Hori ,  Junichi Kato ,  Shinji Odanaka ,  Seiki Ogura

    IPC分类号： H01L21336

    CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L29/42336 ,  H01L29/7885

    摘要： The nonvolatile semiconductor memory device of the present invention includes: a semiconductor substrate having a surface including a first surface region at a first level, a second surface region at a second level lower than the first level, and a step side region linking the first surface region and the second surface region together; a channel region formed in the first surface region of the semiconductor substrate; a source region and a drain region which are formed in the surface of the semiconductor substrate so as to interpose the channel region therebetween; a first insulating film formed on the surface of the semiconductor substrate; a floating gate formed on the first insulating film; and a control gate which is capacitively coupled to the floating gate via a second insulating film. The first insulating film includes a first gate insulating film portion formed in the first surface region, and, a second gate insulating film portion formed in the step side region and the second surface region. The control gate is formed on the first gate insulating film portion. A part of the floating gate faces the step side region via the second gate insulating film portion, and another part of the floating gate is adjacent to the control gate via the second insulating film.

    摘要翻译： 本发明的非易失性半导体存储器件包括：半导体衬底，具有包括第一层的第一表面区域，低于第一层次的第二层的第二表面区域和将第一表面 区域和第二表面区域在一起; 形成在所述半导体衬底的所述第一表面区域中的沟道区; 源极区域和漏极区域，其形成在半导体衬底的表面中，以便在其间插入沟道区域; 形成在所述半导体衬底的表面上的第一绝缘膜; 形成在第一绝缘膜上的浮栅; 以及通过第二绝缘膜电容耦合到浮置栅极的控制栅极。 第一绝缘膜包括形成在第一表面区域中的第一栅极绝缘膜部分和形成在台阶侧区域和第二表面区域中的第二栅极绝缘膜部分。 控制栅极形成在第一栅极绝缘膜部分上。 浮栅的一部分经由第二栅极绝缘膜部分面对台阶侧区域，浮栅的另一部分经由第二绝缘膜与控制栅极相邻。

    Nonvolatile semiconductor memory device and method for fabricating the same and semiconductor integrated circuit
    40.
    发明授权
    Nonvolatile semiconductor memory device and method for fabricating the same and semiconductor integrated circuit 失效
    非易失性半导体存储器件及其制造方法和半导体集成电路

    公开(公告)号：US6121655A

    公开(公告)日：2000-09-19

    申请号：US848

    申请日：1997-12-30

    申请人： Shinji Odanaka ,  Kaori Akamatsu ,  Junichi Kato ,  Atsushi Hori ,  Seiki Ogura

    发明人： Shinji Odanaka ,  Kaori Akamatsu ,  Junichi Kato ,  Atsushi Hori ,  Seiki Ogura

    IPC分类号： G11C16/04 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792 ,  H01L29/76

    CPC分类号： H01L29/66825 ,  H01L29/42324 ,  H01L29/7885

    摘要： The nonvolatile semiconductor memory device of the present invention includes: a semiconductor substrate having a surface including a first surface region at a first level, a second surface region at a second level lower than the first level, and a step side region linking the first surface region and the second surface region together; a channel region formed in the first surface region of the semiconductor substrate; a source region and a drain region which are formed in the surface of the semiconductor substrate so as to interpose the channel region therebetween; a first insulating film formed on the surface of the semiconductor substrate; a floating gate formed on the first insulating film; a second insulating film formed on the floating gate; and a control gate which is capacitively coupled to the floating gate via the second insulating film. The drain region includes a low-concentration impurity layer which is formed in the second surface region and which has one end extending toward the step side region, and a high-concentration impurity layer which is connected to the low-concentration impurity layer and which is formed in a region distant from the channel region. As impurity concentration of the low-concentration impurity layer is lower than an impurity concentration of the high-concentration impurity layer. The floating gate covers the step side region and at least a part of the low-concentration impurity layer via the first insulating film.

    摘要翻译： 本发明的非易失性半导体存储器件包括：半导体衬底，具有包括第一层的第一表面区域，低于第一层次的第二层的第二表面区域和将第一表面 区域和第二表面区域在一起; 形成在所述半导体衬底的所述第一表面区域中的沟道区; 源极区域和漏极区域，其形成在半导体衬底的表面中，以便在其间插入沟道区域; 形成在所述半导体衬底的表面上的第一绝缘膜; 形成在第一绝缘膜上的浮栅; 形成在浮动栅极上的第二绝缘膜; 以及通过第二绝缘膜电容耦合到浮动栅极的控制栅极。 漏区包括形成在第二表面区域中并且具有朝向台阶侧区域延伸的一端的低浓度杂质层和连接到低浓度杂质层的高浓度杂质层， 形成在远离通道区域的区域中。 由于低浓度杂质层的杂质浓度低于高浓度杂质层的杂质浓度。 浮置栅极经由第一绝缘膜覆盖台阶侧区域和至少一部分低浓度杂质层。