公开(公告)号：US11853116B2

公开(公告)日：2023-12-26

申请号：US17582058

申请日：2022-01-24

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Dotan David Levi ,  Wojciech Wasko ,  Eitan Zahavi ,  Natan Manevich ,  Bar Shapira

IPC: G06F1/14 ,  H04J3/06 ,  G06F1/12

CPC classification number: G06F1/14 ,  G06F1/12 ,  H04J3/0661 ,  H04J3/0679 ,  H04J3/0682 ,  H04J3/0697

Abstract: In one embodiment, a device includes a hardware clock to maintain a clock value, a hardware counter to maintain an estimation of a dynamic error bound of the clock value, and a clock controller to intermittently discipline the hardware clock responsively to a remote clock, advance the hardware counter at a rate responsively to a clock drift, and adjust the hardware counter responsively to the hardware clock being disciplined.

公开(公告)号：US20230367358A1

公开(公告)日：2023-11-16

申请号：US17867779

申请日：2022-07-19

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Natan Manevich ,  Dotan David Levi ,  Wojciech Wasko ,  Ariel Almog ,  Bar Shapira

IPC: G06F1/12 ,  G06F1/10 ,  G06F1/06

CPC classification number: G06F1/12 ,  G06F1/10 ,  G06F1/06

Abstract: In one embodiment, a synchronized communication system includes a first network device and a second network device, wherein the first network device includes a first physical hardware clock, and is configured to recover a reference clock time from packets received from a remote clock, find a clock differential between a clock time output by the first physical hardware clock and the recovered reference clock time, provide a control signal to the second network device responsively to the clock differential, and the second network device includes a second physical hardware clock, and is configured to adjust a clock time output by the second physical hardware clock responsively to the control signal.

公开(公告)号：US11641245B2

公开(公告)日：2023-05-02

申请号：US17246730

申请日：2021-05-03

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Dotan David Levi ,  Wojciech Wasko ,  Natan Manevich ,  Roee Moyal ,  Eliel Peretz ,  Eran Ben Elisha ,  Ariel Almog ,  Teferet Geula ,  Amit Mandelbaum

IPC: H04J3/06 ,  H04L43/0817 ,  H04L43/0882 ,  H04L67/55

Abstract: In one embodiment, an event processing system includes a clock configured to provide time values, and event processing circuitry, which is configured to generate a confidence level indicative of a degree of confidence of an accuracy of a timestamp, the timestamp being generated for an event responsively to a time value indicative of when an operation associated with the event occurred.

公开(公告)号：US12294450B2

公开(公告)日：2025-05-06

申请号：US17665600

申请日：2022-02-07

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Dotan David Levi ,  Ioannis (Giannis) Patronas ,  Wojciech Wasko ,  Paraskevas Bakopoulos ,  Dimitrios Syrivelis ,  Elad Mentovich

IPC: H04J14/08 ,  H04J3/06 ,  H04J14/02

Abstract: A network adapter includes a host interface and a scheduler. The host interface is configured to receive, from one or more hosts, packets for transmission to respective destinations over a network. The scheduler is configured to synchronize to a time-division schedule that is employed in the network, the time-division schedule specifying (i) multiple time-slots and (ii) multiple respective groups of the destinations that are reachable during the time-slots, and, based on the time-division schedule, to schedule transmission times of the packets to the network on time-slots during which the respective destinations of the packets are reachable.

公开(公告)号：US12216489B2

公开(公告)日：2025-02-04

申请号：US18111916

申请日：2023-02-21

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Wojciech Wasko ,  Dotan David Levi ,  Natan Manevich ,  Maciek Machnikowski

IPC: G06F1/12 ,  G06F1/08 ,  G06F1/14

Abstract: In one embodiment, a clock synchronization system includes clock circuitry to maintain a clock running at a clock frequency, a clock controller, and a processor to execute software to generate clock update commands and provide the clock update commands to the clock controller, wherein the clock controller is configured to apply the clock update commands to the clock, store a holdover frequency command to maintain the clock during a failure of the clock update commands, apply the holdover frequency command to the clock responsively to detecting the failure.

公开(公告)号：US20240311183A1

公开(公告)日：2024-09-19

申请号：US18479784

申请日：2023-10-02

Applicant: Mellanox Technologies, Ltd.

Inventor： Natan Manevich ,  Ariel Shahar ,  Wojciech Wasko ,  Dotan David Levi ,  Roee Moyal ,  Eliel Peretz

IPC: G06F9/48 ,  G06F9/54

CPC classification number: G06F9/4881 ,  G06F9/542

Abstract: A work descriptor identifying a plurality of workflow tasks to be performed by a hardware device is generated by a host system. A plurality of timestamp logging tasks are added to the work descriptor. Each of the plurality of timestamp logging tasks corresponds to one of the plurality of workflow tasks and instructs the hardware device to log a timestamp in response to an event associated with a respective workflow task. The work descriptor with the plurality of timestamp logging tasks is stored in a work queue of the host system. The work queue is accessible by the hardware device.

公开(公告)号：US20240281022A1

公开(公告)日：2024-08-22

申请号：US18111916

申请日：2023-02-21

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Wojciech Wasko ,  Dotan David Levi ,  Natan Manevich ,  Maciek Machnikowski

IPC: G06F1/12 ,  G06F1/08

CPC classification number: G06F1/12 ,  G06F1/08

Abstract: In one embodiment, a clock synchronization system includes clock circuitry to maintain a clock running at a clock frequency, a clock controller, and a processor to execute software to generate clock update commands and provide the clock update commands to the clock controller, wherein the clock controller is configured to apply the clock update commands to the clock, store a holdover frequency command to maintain the clock during a failure of the clock update commands, apply the holdover frequency command to the clock responsively to detecting the failure.

公开(公告)号：US20240168797A1

公开(公告)日：2024-05-23

申请号：US17988812

申请日：2022-11-17

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Wojciech Wasko ,  Dotan David Levi ,  Harsha Deepak Banuli Nanje Gowda ,  Natan Manevich ,  Daniel Marcovitch

IPC: G06F9/48 ,  G06F1/12 ,  G06F13/40

CPC classification number: G06F9/4881 ,  G06F1/12 ,  G06F13/405

Abstract: In one embodiment, a system includes a peripheral data connection bus configured to connect to devices and transfer data between the devices, a scheduling machine configured to connect to the peripheral data connection bus and send a read request message to a first processing device, and the first processing device configured to be connected to the peripheral data connection bus, and responsively to the read request message add a time value to a read response message, and provide the read response message to the scheduling machine, and wherein the scheduling machine is configured to read the time value from the provided read response message and schedule processing of an operation by a second processing device responsively to the read time value.

公开(公告)号：US20240154783A1

公开(公告)日：2024-05-09

申请号：US17983427

申请日：2022-11-09

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Dotan David Levi ,  Wojciech Wasko

IPC: H04L7/00 ,  H04L7/06 ,  H04L47/62

CPC classification number: H04L7/0008 ,  H04L7/06 ,  H04L47/6225

Abstract: In one embodiment, a system includes a network interface controller to receive a first clock-synchronization message from a clock-synchronization leader device and send a second clock-synchronization messages to at least one clock-synchronization follower device, and a processor to execute software to generate the second clock-synchronization message, and generate a control dependency to condition sending the second clock-synchronization message by the network interface controller to the at least one clock-synchronization follower device on the network interface controller receiving the first clock-synchronization message from the clock-synchronization leader device.

公开(公告)号：US20240089077A1

公开(公告)日：2024-03-14

申请号：US17942899

申请日：2022-09-12

Applicant: Mellanox Technologies, Ltd.

Inventor： Wojciech Wasko ,  Dotan David Levi ,  Natan Manevich ,  Maciek Machnikowski

IPC: H04L7/00 ,  H04L12/18

CPC classification number: H04L7/0091 ,  H04L12/1881

Abstract: A network interface device includes a local register and packet processing circuitry coupled to the local register. The packet processing circuitry is to: capture a network packet transmitted by a software application running on an integrated computing system; capture, at time of transmission of the network packet, a value of a physical clock as a receive timestamp for subscriber entities that are running on the integrated computing system; store the receive timestamp in the local register; associate the receive timestamp from the local register with a first packet copy of the network packet; insert the first packet copy to a first receive pipeline of a first subscriber entity; associate the receive timestamp from the local register with a second packet copy of the network packet; and insert the second packet copy to a second receive pipeline of a second subscriber entity.