公开(公告)号：US06819320B2

公开(公告)日：2004-11-16

申请号：US10090479

申请日：2002-03-04

申请人： Michael G. Lavelle ,  Elena M. Ing

发明人： Michael G. Lavelle ,  Elena M. Ing

IPC分类号： G06F1500

CPC分类号： G06T5/002 ,  G06T5/20 ,  G06T2200/12 ,  G06T2207/10016

摘要： A graphics system and method for storing pixel values into or reading pixel values from a sample buffer, wherein the sample buffer is configured to store a plurality of samples for each of a plurality of pixels. The graphics system comprises a sample buffer, a programmable register, and a graphics processor. The programmable register stores a value indicating a method for pixel to sample conversion, and is preferably software programmable (e.g., user programmable). The graphics processor accesses the memory to determine a method for pixel to sample conversion and stores the pixel values in the sample buffer according to the determined method. A first method for pixel to sample conversion may specify a pixel write to all of the pixel's supporting samples. A second method for pixel to sample conversion may specify a pixel write to a selected one of the pixel's supporting samples.

摘要翻译： 一种用于将像素值存储到样本缓冲器中或从其中读取像素值的图形系统和方法，其中所述采样缓冲器被配置为存储多个像素中的每一个的多个采样。 图形系统包括采样缓冲器，可编程寄存器和图形处理器。 可编程寄存器存储指示用于像素到样本转换的方法的值，并且优选地是软件可编程的（例如，用户可编程的）。 图形处理器访问存储器以确定用于像素进行采样转换的方法，并根据确定的方法将像素值存储在采样缓冲器中。 用于像素进行采样转换的第一种方法可以指定对所有像素的支持样本的像素写入。 用于像素到采样转换的第二种方法可以指定对所选像素的支持样本中的所选择的像素的像素写入。

公开(公告)号：US06795081B2

公开(公告)日：2004-09-21

申请号：US09861479

申请日：2001-05-18

申请人： Michael G. Lavelle ,  Philip C. Leung ,  Yan Y. Tang

发明人： Michael G. Lavelle ,  Philip C. Leung ,  Yan Y. Tang

IPC分类号： G09G536

CPC分类号： G06T1/60

摘要： A system and method capable of super-sampling and performing super-sample convolution are disclosed. In one embodiment, the system may comprise a graphics processor, a frame buffer, a sample cache, and a sample-to-pixel calculation unit. The graphics processor may be configured to generate a plurality of samples. The frame buffer, which is coupled to the graphics processor, may be configured to store the samples in a sample buffer. The samples may be positioned according to a regular grid, a perturbed regular grid, or a stochastic grid. The sample-to-pixel calculation unit is programmable to select a variable number of stored samples from the frame buffer, copy the selected samples to a sample cache, and filter a set of the selected samples into an output pixel. The sample-to-pixel calculation unit retains those samples in the sample cache that will be reused in a subsequent pixel calculation and replaces those samples no longer required with new samples for another filter calculation.

摘要翻译： 公开了能够超采样和执行超采样卷积的系统和方法。 在一个实施例中，系统可以包括图形处理器，帧缓冲器，采样高速缓存和采样到像素计算单元。 图形处理器可以被配置为生成多个采样。 耦合到图形处理器的帧缓冲器可以被配置为将样本存储在采样缓冲器中。 样本可以根据规则网格，扰动的规则网格或随机网格来定位。 样本到像素计算单元是可编程的，以从帧缓冲器中选择可变数量的存储样本，将所选样本复制到样本高速缓存，并将所选择的样本集合过滤到输出像素中。 样本到像素计算单元将样本缓存中保留的样本保留在随后的像素计算中重新使用，并将不再需要的样本替换为另一个滤波器计算的新采样。

公开(公告)号：US06795080B2

公开(公告)日：2004-09-21

申请号：US10060954

申请日：2002-01-30

申请人： Michael G. Lavelle ,  David C. Kehlet ,  Michael A. Wasserman ,  Nandini Ramani ,  Ranjit S. Oberoi

发明人： Michael G. Lavelle ,  David C. Kehlet ,  Michael A. Wasserman ,  Nandini Ramani ,  Ranjit S. Oberoi

IPC分类号： G06T1140

CPC分类号： G06T11/001

摘要： A graphics system configured to apply multiple layers of texture information to batches of primitives. The graphics system collects primitives into a batch that share a common set of texture layers to be applied. The batch is limited so that the total estimate size of the batch is less than or equal to a storage capacity of a texture accumulation buffer. The graphics system stores samples (or fragments) corresponding to the batch primitives in the texture accumulation buffer between the application of successive texture layers.

摘要翻译： 图形系统被配置为将多层纹理信息应用于批量的图元。 图形系统将基元收集到共享要应用的一组公共纹理图层的批次中。 批量被限制，使得批次的总估计大小小于或等于纹理累积缓冲器的存储容量。 图形系统将相应于批量原语的样本（或片段）存储在连续纹理层的应用之间的纹理累积缓冲器中。

公开(公告)号：US06670959B2

公开(公告)日：2003-12-30

申请号：US09861481

申请日：2001-05-18

申请人： Michael A. Wasserman ,  Michael G. Lavelle ,  David C. Kehlet ,  Glenn Gracon

发明人： Michael A. Wasserman ,  Michael G. Lavelle ,  David C. Kehlet ,  Glenn Gracon

IPC分类号： G06F1318

CPC分类号： G09G5/001 ,  G06F3/1431 ,  G06F13/1605 ,  G09G3/003 ,  G09G5/006 ,  G09G5/346 ,  G09G5/393 ,  G09G5/395 ,  G09G2360/128 ,  G09G2360/18

摘要： A graphics system that may be shared between multiple display channels includes a frame buffer, an arbiter, and two pixel output buffers. The arbiter arbitrates between the display channels' requests for display information from the frame buffer and forwards a selected request to the frame buffer. The frame buffer is divided into a first and a second portion. The arbiter alternates display channel requests for data between the first and second portions of the frame buffer. The frame buffer outputs display information in response to receiving the forwarded request, and pixels corresponding to this display information are stored in the output buffers. The arbiter selects which request to forward to the frame buffer based on a relative state of neediness of each of the requesting display channels.

摘要翻译： 可以在多个显示通道之间共享的图形系统包括帧缓冲器，仲裁器和两个像素输出缓冲器。 仲裁者在显示通道对帧缓冲器的显示信息请求之间进行仲裁，并将所选择的请求转发到帧缓冲器。 帧缓冲器被分成第一和第二部分。 仲裁器交替显示帧缓冲器的第一和第二部分之间的数据的信道请求。 帧缓冲器响应于接收转发的请求而输出显示信息，并且与该显示信息相对应的像素被存储在输出缓冲器中。 仲裁器根据每个请求显示通道的相关状态选择哪个请求转发到帧缓冲器。

公开(公告)号：US06654021B2

公开(公告)日：2003-11-25

申请号：US09861461

申请日：2001-05-18

申请人： Michael A. Wasserman ,  Michael G. Lavelle ,  David C. Kehlet ,  Nathaniel David Naegle ,  Steven Te-Chun Yu ,  Glenn Gracon

发明人： Michael A. Wasserman ,  Michael G. Lavelle ,  David C. Kehlet ,  Nathaniel David Naegle ,  Steven Te-Chun Yu ,  Glenn Gracon

IPC分类号： G06F1318

CPC分类号： G09G5/12 ,  G06F3/1431 ,  G09G5/395 ,  G09G2360/123

摘要： A graphics system that may be shared between multiple display channels includes a frame buffer, two arbiters, a pixel buffer, and several display output queues. The first arbiter arbitrates between the display channels' requests for display information from the frame buffer and forwards a selected request to the frame buffer. The frame buffer outputs display information in response to receiving the forwarded request, and pixels corresponding to this display information are stored in the pixel buffer. Each display channel has a corresponding display output queue that provides data to a display and generates a request for pixels from the pixel buffer. A pixel request arbiter receives the pixel requests generated by the display output queues, selects one of the pixel requests, and forwards the selected request to the pixel buffer. In response, the pixel buffer outputs pixels to the display output queue that generated the selected pixel request.

公开(公告)号：US07599439B2

公开(公告)日：2009-10-06

申请号：US11166458

申请日：2005-06-24

申请人： Michael G. Lavelle ,  Paul Daniel Wolf

发明人： Michael G. Lavelle ,  Paul Daniel Wolf

IPC分类号： H04N7/18

CPC分类号： G06F3/14 ,  G09G3/2092 ,  G09G5/006

摘要： A system including a receiver, a TMDS link (or other serial link), and a transmitter configured to transmit K-bit video words (typically, encoded 8-bit video words) over the link. In typical embodiments, the transmitter is configured to pack a sequence of N-bit video words, where N≠K (e.g., N=10, 12, or 16, when K=8) into a sequence of K-bit fragments, encode the fragments, and transmit the encoded fragments. The transmitted data are indicative of a sequence of M-fragment groups, and the transmitter is typically configured also to transmit over the link packing phase data indicative of the phase of the most recently transmitted fragment. Other aspects are transmitters and receivers for use in such a system and methods implemented by any such transmitter, receiver, or system.

摘要翻译： 包括接收机，TMDS链路（或其他串行链路）的系统和被配置为通过链路发送K位视频字（通常为编码的8位视频字）的发射机。 在典型的实施例中，发射机被配置为将N个比特视频字序列打包到一个K比特片段序列中，其中N

公开(公告)号：US06859209B2

公开(公告)日：2005-02-22

申请号：US09861468

申请日：2001-05-18

申请人： Michael G. Lavelle ,  Brian D. Emberling ,  Ranjit S. Oberoi ,  Deron D. Johnson ,  Ewa M. Kubalska

发明人： Michael G. Lavelle ,  Brian D. Emberling ,  Ranjit S. Oberoi ,  Deron D. Johnson ,  Ewa M. Kubalska

IPC分类号： G06T15/00 ,  G09G5/36 ,  G09G5/00

CPC分类号： G09G5/363 ,  G06T11/40 ,  G06T15/005

摘要： A graphics system applies multiple layers of texture information to triangles. The graphics system includes a hardware accelerator, a frame buffer and a video output processor. The hardware accelerator receives vertices of a triangle, identifies fragments of a sampling space which intersect the triangle, and applies the multiple layers of texture to the intersecting fragments. The multiple layers of textures may be stored in a texture memory external to the hardware accelerator. The hardware accelerator switches to a next texture layer after applying the textures of a current layer to all the fragments of the triangle. The hardware accelerator includes (or couples to) a texture accumulation buffer which stores color values associated with the triangle fragments between the application of successive texture layers. The frame buffer stores the samples and pixels generated from the samples by filtration. The video output processor transforms the pixels into a video signal.

摘要翻译： 图形系统将多层纹理信息应用于三角形。 图形系统包括硬件加速器，帧缓冲器和视频输出处理器。 硬件加速器接收三角形的顶点，识别与三角形相交的采样空间的片段，并将多层纹理应用于相交片段。 多层纹理可以存储在硬件加速器外部的纹理存储器中。 硬件加速器在将当前层的纹理应用于三角形的所有片段之后切换到下一个纹理层。 硬件加速器包括（或耦合到）纹理累积缓冲器，其存储与连续纹理层的应用之间的三角形片段相关联的颜色值。 帧缓冲器通过过滤存储从样本产生的样本和像素。 视频输出处理器将像素转换为视频信号。

公开(公告)号：US06836272B2

公开(公告)日：2004-12-28

申请号：US10096066

申请日：2002-03-12

申请人： Philip C. Leung ,  Michael G. Lavelle ,  Elena M. Ing

发明人： Philip C. Leung ,  Michael G. Lavelle ,  Elena M. Ing

IPC分类号： G09G5399

CPC分类号： G09G5/39 ,  G09G5/14 ,  G09G2360/121 ,  G09G2360/126

摘要： A graphics system includes a frame buffer that includes one or more memory devices and a frame buffer interface coupled to the frame buffer. Each memory device in the frame buffer includes N banks. Each of the N banks includes multiple pages, and each page is configured to store data corresponding to a portion of a screen region. The frame buffer interface is configured to generate address used to store data corresponding to a frame of data in the frame buffer. The frame includes multiple screen regions. The frame buffer interface is configured to generate addresses corresponding to the data and to provide the addresses to the frame buffer. The addresses are generated such that each of the N banks stores data corresponding to a portion of one out of every N screen regions within a horizontal group of screen regions.

摘要翻译： 图形系统包括帧缓冲器，其包括一个或多个存储器设备和耦合到帧缓冲器的帧缓冲器接口。 帧缓冲器中的每个存储器件包括N个存储体。 每个N个存储体包括多个页面，并且每个页面被配置为存储对应于屏幕区域的一部分的数据。 帧缓冲器接口被配置为生成用于存储对应于帧缓冲器中的数据帧的数据的地址。 该框架包括多个屏幕区域。 帧缓冲器接口被配置为生成与该数据相对应的地址，并且向帧缓冲器提供地址。 生成地址，使得N个存储体中的每一个存储对应于屏幕区域的水平组内的每N个屏幕区域中的一个的一部分的数据。

公开(公告)号：US06803916B2

公开(公告)日：2004-10-12

申请号：US09861475

申请日：2001-05-18

申请人： Nandini Ramani ,  David C. Kehlet ,  Ewa M. Kubalska ,  Michael G. Lavelle ,  Michael A. Wasserman ,  Kevin Tang ,  Yan Yan Tang

发明人： Nandini Ramani ,  David C. Kehlet ,  Ewa M. Kubalska ,  Michael G. Lavelle ,  Michael A. Wasserman ,  Kevin Tang ,  Yan Yan Tang

IPC分类号： G06T120

CPC分类号： G06T15/00 ,  G06T11/40

摘要： A system and method for rasterizing and rendering graphics data is disclosed. Vertices may be grouped to form primitives such as triangles, which are rasterized using two-dimensional arrays of samples bins. Individual samples may be selected from the bins according to different criteria such as memory bank allocation to improve utilization of the system's rendering pipeline. Since the arrays may have more bins than the number of evaluation units in the rendering pipeline, the samples from the bins may be stored to FIFO memories to allow invalid or empty samples (those outside the primitive being rendered) to be removed. The samples may then be filtered to form pixels that are displayable to form an image on a display device.

摘要翻译： 公开了一种用于光栅化和渲染图形数据的系统和方法。 顶点可以被分组以形成诸如三角形的图元，其使用样本仓的二维阵列进行光栅化。 可以根据诸如存储体分配的不同标准从箱中选择单个样本，以提高系统的渲染管线的利用率。 由于阵列可以具有比渲染流水线中的评估单元数更多的存储单元，所以来自存储区的样本可以被存储到FIFO存储器中以允许去除无效或空的样本（被渲染的原始图像之外的样本）。 然后可以对样本进行滤波以形成可显示以在显示装置上形成图像的像素。

公开(公告)号：US06778179B2

公开(公告)日：2004-08-17

申请号：US09970113

申请日：2001-10-03

申请人： Michael G. Lavelle ,  Ewa M. Kubalska ,  Yan Yan Tang

发明人： Michael G. Lavelle ,  Ewa M. Kubalska ,  Yan Yan Tang

IPC分类号： G09G536

CPC分类号： G06F12/0897 ,  G06T1/60 ,  G06T15/005 ,  G09G5/363 ,  G09G5/39 ,  G09G2360/121 ,  G09G2360/122 ,  Y02D10/13

摘要： An external cache management unit for use with a 3D-RAM frame buffer and suitable for use in a computer graphics system is described. The unit may reduce power consumption within the 3D-RAM by performing partial block write-back according to status information stored in an array of dirty tag bits. Periodic level one cache block cleansing is provided for during empty memory cycles.

摘要翻译： 描述了一种用于3D-RAM帧缓冲器并适用于计算机图形系统的外部高速缓存管理单元。 该单元可以通过根据存储在脏标签位阵列中的状态信息执行部分块回写来减少3D-RAM内的功耗。 在空的存储器循环期间提供了周期性的一级缓存块清理。