公开(公告)号：US20200303363A1

公开(公告)日：2020-09-24

申请号：US16805341

申请日：2020-02-28

Applicant: Micron Technology, Inc.

Inventor： Chan H. Yoo ,  Owen R. Fay

IPC: H01L25/18 ,  H01L23/00 ,  H01L21/78 ,  H01L25/00

Abstract: An interposer comprises a semiconductor material and includes cache memory under a location on the interposer for a host device. Memory interface circuitry may also be located under one or more locations on the interposer for memory devices. Microelectronic device assemblies incorporating such an interposer and comprising a host device and multiple memory devices are also disclosed, as are methods of fabricating such microelectronic device assemblies.

公开(公告)号：US10586780B2

公开(公告)日：2020-03-10

申请号：US16397800

申请日：2019-04-29

Applicant: Micron Technology, Inc.

Inventor： Ashok Pachamuthu ,  Chan H. Yoo ,  Szu-Ying Ho ,  John F. Kaeding

IPC: H01L23/34 ,  H01L21/00 ,  H01L23/00 ,  H01L21/768 ,  H01L25/00 ,  H01L21/56 ,  H01L21/683 ,  H01L25/065 ,  H01L23/31 ,  H01L23/538 ,  H01L23/498 ,  H01L21/48

Abstract: Semiconductor device modules may include a semiconductor die and posts located laterally adjacent to the semiconductor die. A first encapsulant may laterally surround the semiconductor die and the posts. Electrical connectors may extend laterally from the posts, over the first encapsulant, to bond pads on an active surface of the semiconductor die. A protective material may cover the electrical connectors. A second encapsulant may cover the protective material and the electrical connectors. The second encapsulant may be in direct contact with the first encapsulant, the electrical connectors, and the protective material.

公开(公告)号：US20190304860A1

公开(公告)日：2019-10-03

申请号：US16447835

申请日：2019-06-20

Applicant: Micron Technology, Inc.

Inventor： Chan H. Yoo ,  Mark E. Tuttle

IPC: H01L23/18 ,  H01L23/31 ,  H01L23/00 ,  H01L21/66 ,  H01L23/373 ,  H01L23/16

Abstract: A semiconductor device assembly including a substrate, a semiconductor device, a stiffener member, and mold compound. The stiffener member is tuned, or configured, to reduce and/or control the shape of warpage of the semiconductor device assembly at an elevated temperature. The stiffener member may be placed on the substrate, on the semiconductor device, and/or on the mold compound. A plurality of stiffener members may be used. The stiffener members may be positioned in a predetermined pattern on a component of the semiconductor device assembly. A stiffener member may be used so that the warpage of a first semiconductor device substantially corresponds to the warpage of a second semiconductor device at an elevated temperature. The stiffener member may be tuned by providing the member with a desired coefficient of thermal expansion (CTE). The desired CTE may be based on the individual CTEs of the components of a semiconductor device assembly.

公开(公告)号：US10396003B2

公开(公告)日：2019-08-27

申请号：US15787321

申请日：2017-10-18

Applicant: Micron Technology, Inc.

Inventor： Chan H. Yoo ,  Mark E. Tuttle

IPC: H01L23/31 ,  H01L21/66 ,  H01L23/18 ,  H01L23/373 ,  H01L23/16 ,  H01L23/00

Abstract: A semiconductor device assembly including a substrate, a semiconductor device, a stiffener member, and mold compound. The stiffener member is tuned, or configured, to reduce and/or control the shape of warpage of the semiconductor device assembly at an elevated temperature. The stiffener member may be placed on the substrate, on the semiconductor device, and/or on the mold compound. A plurality of stiffener members may be used. The stiffener members may be positioned in a predetermined pattern on a component of the semiconductor device assembly. A stiffener member may be used so that the warpage of a first semiconductor device substantially corresponds to the warpage of a second semiconductor device at an elevated temperature. The stiffener member may be tuned by providing the member with a desired coefficient of thermal expansion (CTE). The desired CTE may be based on the individual CTEs of the components of a semiconductor device assembly.

公开(公告)号：US20190067247A1

公开(公告)日：2019-02-28

申请号：US15686024

申请日：2017-08-24

Applicant: Micron Technology, Inc.

Inventor： Chan H. Yoo ,  Mark E. Tuttle

IPC: H01L25/065 ,  H01L25/00

Abstract: Semiconductor devices including a dual-sided redistribution structure and having low-warpage across all temperatures and associated systems and methods are disclosed herein. In one embodiment, a semiconductor device includes a first semiconductor die electrically coupled to a first side of a redistribution structure and a second semiconductor die electrically coupled to a second side of the redistribution structure opposite the first side. The semiconductor device also includes a first molded material on the first side, a second molded material on the second side, and conductive columns electrically coupled to the first side and extending through the first molded material. The first and second molded materials can have the same volume and/or coefficients of thermal expansion to inhibit warpage of the semiconductor device.

公开(公告)号：US20190067233A1

公开(公告)日：2019-02-28

申请号：US16175449

申请日：2018-10-30

Applicant: Micron Technology, Inc.

Inventor： Ashok Pachamuthu ,  Chan H. Yoo ,  Szu-Ying Ho ,  John F. Kaeding

IPC: H01L23/00 ,  H01L23/31 ,  H01L25/065 ,  H01L21/56 ,  H01L21/683 ,  H01L25/00 ,  H01L21/768

Abstract: Semiconductor device modules may include a redistribution layer and a first semiconductor die. A second semiconductor die may be located on the first semiconductor die. Posts may be located laterally adjacent to the first semiconductor die and the second semiconductor die. A first encapsulant may at least laterally surround the first semiconductor die, the second semiconductor die, and the posts. Electrical connectors may extend laterally from the posts, over the first encapsulant, to bond pads on a second active surface of the second semiconductor die. A protective material may cover the electrical connectors. A second encapsulant may be located over the protective material and the electrical connectors. The second encapsulant may be in direct contact with the first encapsulant, the electrical connectors, and the protective material. Conductive bumps may be connected to the redistribution layer on a side of the redistribution layer opposite the first semiconductor die.

公开(公告)号：US10192843B1

公开(公告)日：2019-01-29

申请号：US15660442

申请日：2017-07-26

Applicant: Micron Technology, Inc.

Inventor： Ashok Pachamuthu ,  Chan H. Yoo ,  Szu-Ying Ho ,  John F. Kaeding

IPC: H01L23/34 ,  H01L21/00 ,  H01L23/00 ,  H01L21/768 ,  H01L25/00 ,  H01L21/56 ,  H01L21/683 ,  H01L25/065 ,  H01L23/31

Abstract: Methods of making semiconductor device modules may involve forming holes in a sacrificial material and placing an electrically conductive material in the holes. The sacrificial material may be removed to expose posts of the electrically conductive material. A stack of semiconductor dice may be placed between at least two of the posts after removing the sacrificial material, one of the semiconductor dice of the stack including an active surface facing in a direction opposite a direction in which another active surface of another of the semiconductor dice of the stack. The posts and the stack of semiconductor dice may be at least laterally encapsulated in an encapsulant. Bond pads of the one of the semiconductor dice may be electrically connected to corresponding posts after at least laterally encapsulating the posts and the stack of semiconductor dice.

公开(公告)号：US12277056B2

公开(公告)日：2025-04-15

申请号：US18215474

申请日：2023-06-28

Applicant: Micron Technology, Inc.

Inventor： Brent Keeth ,  Owen Fay ,  Chan H. Yoo ,  Roy E. Greeff ,  Matthew B. Leslie

IPC: G06F12/06 ,  G06F12/02 ,  G11C11/4093 ,  G11C29/12 ,  H01L25/065 ,  H01L25/18

Abstract: Apparatus and methods are disclosed, including memory devices and systems. Example memory devices, systems and methods include a buffer interface to translate high speed data interactions on a host interface side into slower, wider data interactions on a DRAM interface side. The slower, and wider DRAM interface may be configured to substantially match the capacity of the narrower, higher speed host interface. In some examples, the buffer interface may be configured to provide multiple sub-channel interfaces each coupled to one or more regions within the memory structure and configured to facilitate data recovery in the event of a failure of some portion of the memory structure. Selected example memory devices, systems and methods include an individual DRAM die, or one or more stacks of DRAM dies coupled to a buffer die.

公开(公告)号：US12199068B2

公开(公告)日：2025-01-14

申请号：US17817690

申请日：2022-08-05

Applicant: Micron Technology, Inc.

Inventor： Owen R. Fay ,  Randon K. Richards ,  Aparna U. Limaye ,  Dong Soon Lim ,  Chan H. Yoo ,  Bret K. Street ,  Eiichi Nakano ,  Shijian Luo

IPC: H01L25/065 ,  H01L21/66 ,  H01L21/78 ,  H01L23/00 ,  H01L23/552 ,  H01L23/64 ,  H01L23/66 ,  H01L25/00 ,  H01L25/18 ,  H01Q1/22 ,  H01Q1/48

Abstract: Disclosed is a microelectronic device assembly comprising a substrate having conductors exposed on a surface thereof. Two or more microelectronic devices are stacked on the substrate, each microelectronic device comprising an active surface having bond pads operably coupled to conductive traces extending over a dielectric material to via locations beyond at least one side of the stack, and vias extending through the dielectric materials at the via locations and comprising conductive material in contact with at least some of the conductive traces of each of the two or more electronic devices and extending to exposed conductors of the substrate. Methods of fabrication and related electronic systems are also disclosed.

公开(公告)号：US12199001B2

公开(公告)日：2025-01-14

申请号：US18200173

申请日：2023-05-22

Applicant: Micron Technology, Inc.

Inventor： Chan H. Yoo ,  Owen R. Fay

IPC: H01L23/36 ,  H01L23/00 ,  H01L23/42 ,  H01L23/498 ,  H01L25/00 ,  H01L25/065 ,  H01L25/10 ,  H05K7/20

Abstract: Semiconductor assemblies including thermal management configurations for reducing heat transfer between overlapping devices and associated systems and methods are disclosed herein. A semiconductor assembly may comprise a first device and a second device with a thermal management layer disposed between the first and second devices. The thermal management layer may be configured to reduce heat transfer between the first and second devices.