公开(公告)号：US20230008292A1

公开(公告)日：2023-01-12

申请号：US17932401

申请日：2022-09-15

Applicant: Micron Technology, Inc.

Inventor： Randon K. Richards ,  Aparna U. Limaye ,  Owen R. Fay ,  Dong Soon Lim

IPC: H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L23/552 ,  H01L23/64 ,  H01L21/78 ,  H01L21/66 ,  H01L25/00 ,  H01L23/66 ,  H01Q1/22 ,  H01Q1/48

Abstract: Disclosed is a microelectronic device assembly comprising a substrate having conductors exposed on a surface thereof. Two or more microelectronic devices are stacked on the substrate and the components are connected with conductive material in preformed holes in dielectric material in the bond lines aligned with TSVs of the devices and the exposed conductors of the substrate. Methods of fabrication are also disclosed.

公开(公告)号：US11514959B2

公开(公告)日：2022-11-29

申请号：US17193955

申请日：2021-03-05

Applicant: Micron Technology, Inc.

Inventor： Randon K. Richards ,  Dirgha Khatri

IPC: G11C7/22 ,  G11C8/18 ,  G06F13/16 ,  G11C11/4076 ,  G11C11/4093

Abstract: Methods, systems, and apparatuses for managing clock signals at a memory device are described. A memory device or other component of a memory module or electronic system may offset a received clock signal. For example, the memory device may receive a clock signal that has a nominal speed or frequency of operation for a system, and the memory device may adjust or offset the clock signal based on other operating factors, such as the speed or frequency of other signals, physical constraints, indications received from a host device, or the like. A clock offset value may be based on propagation of, for example, command/address signaling. In some examples, a memory module may include a registering clock driver (RCD), hub, or local controller that may manage or coordinate clock offsets among or between various memory devices on the module. Clock offset values may be programmed to a mode register or registers.

公开(公告)号：US20220375902A1

公开(公告)日：2022-11-24

申请号：US17817690

申请日：2022-08-05

Applicant: Micron Technology, Inc.

Inventor： Owen R. Fay ,  Randon K. Richards ,  Aparna U. Limaye ,  Dong Soon Lim ,  Chan H. Yoo ,  Bret K. Street ,  Eiichi Nakano ,  Shijian Luo

IPC: H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L23/552 ,  H01L23/64 ,  H01L21/78 ,  H01L21/66 ,  H01L25/00 ,  H01L23/66 ,  H01Q1/22 ,  H01Q1/48

Abstract: Disclosed is a microelectronic device assembly comprising a substrate having conductors exposed on a surface thereof. Two or more microelectronic devices are stacked on the substrate, each microelectronic device comprising an active surface having bond pads operably coupled to conductive traces extending over a dielectric material to via locations beyond at least one side of the stack, and vias extending through the dielectric materials at the via locations and comprising conductive material in contact with at least some of the conductive traces of each of the two or more electronic devices and extending to exposed conductors of the substrate. Methods of fabrication and related electronic systems are also disclosed.

公开(公告)号：US20220335000A1

公开(公告)日：2022-10-20

申请号：US17850927

申请日：2022-06-27

Applicant: Micron Technology, Inc.

Inventor： Thomas H. Kinsley ,  George E. Pax ,  Timothy M. Hollis ,  Yogesh Sharma ,  Randon K. Richards ,  Chan H. Yoo ,  Gregory A. King ,  Eric J. Stave

IPC: G06F13/42 ,  G06F11/10 ,  G11C7/10

Abstract: An apparatus is provided, comprising a plurality of memory devices and a buffering device that permits memory devices with a variety of physical dimensions and memory formats to be used in an industry-standard memory module format. The buffering device includes memory interface circuitry and at least one first-in first-out (FIFO) or multiplexer circuit. The apparatus further comprises a parallel bus connecting the buffering device to the plurality of memory devices. The parallel bus includes a plurality of independent control lines, each coupling the memory interface circuitry to a corresponding subset of a plurality of first subsets of the plurality of memory devices. The parallel bus further includes a plurality of independent data channels, each coupling the at least one FIFO circuit or multiplexer circuit to a corresponding subset of a plurality of second subsets of the plurality of memory devices.

公开(公告)号：US20220302090A1

公开(公告)日：2022-09-22

申请号：US17805818

申请日：2022-06-07

Applicant: Micron Technology, Inc

Inventor： Aparna U. Limaye ,  Dong Soon Lim ,  Randon K. Richards ,  Owen R. Fay

IPC: H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L23/552 ,  H01L23/64 ,  H01L21/78 ,  H01L21/66 ,  H01L25/00 ,  H01L23/66 ,  H01Q1/22 ,  H01Q1/48

Abstract: Disclosed is a microelectronic device assembly comprising a substrate having conductors exposed on a surface thereof. Two or more stacks of microelectronic devices are located on the substrate, and microelectronic devices of the stacks are connected to vertical conductive paths external to the stacks and extending to the substrate and to lateral conductive paths extending between the stacks. Methods of fabrication are also disclosed.

公开(公告)号：US11177222B2

公开(公告)日：2021-11-16

申请号：US16524989

申请日：2019-07-29

Applicant: Micron Technology, Inc.

Inventor： Owen R. Fay ,  Dong Soon Lim ,  Randon K. Richards ,  Aparna U. Limaye

IPC: H01L23/58 ,  H01L23/552 ,  H01L23/66 ,  H01L23/31 ,  H01L21/56 ,  H01Q1/22

Abstract: Semiconductor devices with antennas and electromagnetic interference (EMI) shielding, and associated systems and methods, are described herein. In one embodiment, a semiconductor device includes a semiconductor die coupled to a package substrate. An antenna structure is disposed over and/or adjacent the semiconductor die. An electromagnetic interference (EMI) shield is disposed between the semiconductor die and the antenna structure to shield at least the semiconductor die from electromagnetic radiation generated by the antenna structure and/or to shield the antenna structure from interference generated by the semiconductor die. A first dielectric material and/or a thermal interface material can be positioned between the semiconductor die and the EMI shield, and a second dielectric material can be positioned between the EMI shield and the antenna structure. In some embodiments, the semiconductor device includes a package molding over at least a portion of the antenna, the EMI shield, and/or the second dielectric material.

公开(公告)号：US10989748B2

公开(公告)日：2021-04-27

申请号：US16931912

申请日：2020-07-17

Applicant: Micron Technology, Inc.

Inventor： Paul E. Gregory ,  Randon K. Richards

IPC: G01R31/00 ,  G01R31/44 ,  G01R1/067

Abstract: The present disclosure includes apparatuses and methods related to test devices, for example testing devices by measuring signals emitted by a device. One example apparatus can include a first portion including a number of sidewalls positioned to at least partially surround a device under test; and a second portion electrically coupled to the first portion, wherein the second portion is configured to move in the x-direction, the y-direction, and z-direction.

公开(公告)号：US11410973B2

公开(公告)日：2022-08-09

申请号：US16939756

申请日：2020-07-27

Applicant: Micron Technology, Inc.

Inventor： Owen R. Fay ,  Randon K. Richards ,  Aparna U. Limaye ,  Dong Soon Lim ,  Chan H. Yoo ,  Bret K. Street ,  Eiichi Nakano ,  Shijian Luo

IPC: H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L23/552 ,  H01L23/64 ,  H01L21/78 ,  H01L21/66 ,  H01L25/00 ,  H01L23/66 ,  H01Q1/22 ,  H01Q1/48

Abstract: Disclosed is a microelectronic device assembly comprising a substrate having conductors exposed on a surface thereof. Two or more microelectronic devices are stacked on the substrate, each microelectronic device comprising an active surface having bond pads operably coupled to conductive traces extending over a dielectric material to via locations beyond at least one side of the stack, and vias extending through the dielectric materials at the via locations and comprising conductive material in contact with at least some of the conductive traces of each of the two or more electronic devices and extending to exposed conductors of the substrate. Methods of fabrication and related electronic systems are also disclosed.

公开(公告)号：US20220068837A1

公开(公告)日：2022-03-03

申请号：US17524473

申请日：2021-11-11

Applicant: Micron Technology, Inc.

Inventor： Owen R. Fay ,  Dong Soon Lim ,  Randon K. Richards ,  Aparna U. Limaye

IPC: H01L23/552 ,  H01L23/66 ,  H01L23/31 ,  H01L21/56 ,  H01Q1/22

Abstract: Semiconductor devices with antennas and electromagnetic interference (EMI) shielding, and associated systems and methods, are described herein. In one embodiment, a semiconductor device includes a semiconductor die coupled to a package substrate. An antenna structure is disposed over and/or adjacent the semiconductor die. An electromagnetic interference (EMI) shield is disposed between the semiconductor die and the antenna structure to shield at least the semiconductor die from electromagnetic radiation generated by the antenna structure and/or to shield the antenna structure from interference generated by the semiconductor die. A first dielectric material and/or a thermal interface material can be positioned between the semiconductor die and the EMI shield, and a second dielectric material can be positioned between the EMI shield and the antenna structure. In some embodiments, the semiconductor device includes a package molding over at least a portion of the antenna, the EMI shield, and/or the second dielectric material.

公开(公告)号：US20210036125A1

公开(公告)日：2021-02-04

申请号：US16530757

申请日：2019-08-02

Applicant: Micron Technology, Inc.

Inventor： Chan H. Yoo ,  George E. Pax ,  Yogesh Sharma ,  Gregory A. King ,  Thomas H. Kinsley ,  Randon K. Richards

IPC: H01L29/66 ,  H05K1/11 ,  H01L23/495

Abstract: Systems, apparatuses, and methods relating to memory devices and packaging are described. A device, such as a dual inline memory module (DIMM) or other electronic device package, may include a substrate with a layer of graphene configured to conduct thermal energy (e.g., heat) away from components mounted or affixed to the substrate. In some examples, a DIMM includes an uppermost or top layer of graphene that is exposed to the air and configured to allow connection of memory devices (e.g., DRAMs) to be soldered to the conducting pads of the substrate. The graphene may be in contact with parts of the memory device other than the electrical connections with the conducting pads and may thus be configured as a heat sink for the device. Other thin, conductive layers of may be used in addition to or as an alternative to graphene. Graphene may be complementary to other heat sink mechanisms.