公开(公告)号：US11768613B2

公开(公告)日：2023-09-26

申请号：US16452333

申请日：2019-06-25

Applicant: Micron Technology, Inc.

Inventor： Poorna Kale ,  Christopher Joseph Bueb ,  Taufique Murad Ahmed ,  Sven Lehsten

IPC: G06F3/06 ,  G06F12/02

CPC classification number: G06F3/0626 ,  G06F3/0646 ,  G06F3/0679 ,  G06F12/0246 ,  G06F12/0284

Abstract: A solid state drive having a drive aggregator configured to interface with a host system, and a plurality of component solid state drives connected to the drive aggregator. Each of the component solid state drives has a controller capable of processing commands from host systems. The drive aggregator is configured to receive commands from the host system and transmit commands to the component solid state drives to implement the commands received from the host system.

公开(公告)号：US11711488B2

公开(公告)日：2023-07-25

申请号：US17463408

申请日：2021-08-31

Applicant: Micron Technology, Inc.

Inventor： Poorna Kale ,  Christopher Joseph Bueb ,  Te-Chang Lin ,  Qi Dong

IPC: H04N5/77 ,  G06F12/1009 ,  H04N5/91 ,  H04N7/18 ,  G06F3/0484

CPC classification number: H04N5/77 ,  G06F12/1009 ,  H04N5/91 ,  H04N7/183 ,  G06F3/0484 ,  G06F2212/657

Abstract: A memory system having multiple address tables to translate logical addresses to physical addresses at different granularity levels is disclosed. For example, a first address table is associated with a first block size of translating logical addresses for accessing system files and application files; and a second address table is associated with a second block size of translating logical addresses for storing and/or retrieving data from an image sensor of a surveillance camera. A user interface can be used to access a configuration option to specify the second block size; and a user may indicate a typical size of an image or video file to be recorded by the surveillance camera to calculate the second block size and thus configure the second address table for a partition to record the image or video files.

公开(公告)号：US20230086763A1

公开(公告)日：2023-03-23

申请号：US18059321

申请日：2022-11-28

Applicant: Micron Technology, Inc.

Inventor： Poorna Kale ,  Christopher Joseph Bueb

IPC: G06F11/16 ,  G06F3/06 ,  G06F12/02 ,  G06F11/10

Abstract: A solid state drive having a drive aggregator and a plurality of component solid state drive, including a first component solid state drive and a second component solid state drive. The drive aggregator has at least one host interface, and a plurality of drive interfaces connected to the plurality of component solid state drives. The drive aggregator is configured to generate, in the second solid state drive, a copy of a dataset that is stored in the first component solid state drive. In response to a failure of the first component solid state drive, the drive aggregator is configured to substitute a function of the first component solid state drive with respect to the dataset with a corresponding function of the second component solid state drive, based on the copy of the dataset generated in the second component solid state drive.

公开(公告)号：US20230066561A1

公开(公告)日：2023-03-02

申请号：US17463397

申请日：2021-08-31

Applicant: Micron Technology, Inc.

Inventor： Poorna Kale ,  Christopher Joseph Bueb

IPC: G06F12/02 ,  G06F12/06 ,  G06F3/06

Abstract: A technique to control write operations in a logical partition. For example, a device can receive a user specified write threshold for the logical partition that is hosted on a pool of memory cells shared by a plurality of logical partitions in wear leveling. An accumulated amount of data written into the memory cells according to write requests addressing the logical partition is tracked. In response to the accumulated amount reaches the write threshold, further write requests addressing the logical partition can be blocked, rejected, and/or ignored. For example, the logical partition can be used to buffer data for time shift in playing back content streaming from a server. Write operations for time shift can be limited via the user specified threshold to prevent overuse of the total program erasure budget of the pool of memory cells shared with other logical partitions.

公开(公告)号：US20230041983A1

公开(公告)日：2023-02-09

申请号：US17811230

申请日：2022-07-07

Applicant: Micron Technology, Inc.

Inventor： Christopher Joseph Bueb ,  Minjian Wu

IPC: G11C11/406 ,  G11C11/4072

Abstract: Methods, systems, and devices supporting an interface for refreshing non-volatile memory are described. In some examples, a host system may communicate with a memory system, where both the host system and the memory system may be included within a vehicle (e.g., an automotive system). The host system may receive an indication that the vehicle is powering down (e.g., shutting off an engine or lowering power output from a battery). The host system may switch from a first mode corresponding to a first power usage to a second mode corresponding to a second, lower power usage in response to the vehicle powering down, the second mode supporting initiation of a refresh operation at the memory device. The host system may transmit a refresh command to the memory system to refresh non-volatile memory while the vehicle is powered down if the host system is operating in the second mode of operation.

公开(公告)号：US20210312273A1

公开(公告)日：2021-10-07

申请号：US16840233

申请日：2020-04-03

Applicant: Micron Technology, Inc.

Inventor： Poorna Kale ,  Christopher Joseph Bueb

IPC: G06N3/08 ,  G06N3/063 ,  G06N5/04 ,  G06K9/62 ,  G06F17/16 ,  B60W60/00

Abstract: Systems, methods and apparatuses of processing overwhelming stimuli in vehicle data recorders. For example, a data recorder can have resources, such as memory components, a controller, an inference engine, etc. The resources can be partitioned into a first subset and a second subset. Abnormal stimuli in an input stream to the recorder may cause delay for real time processing. In response, a time sliced segment of the input stream is selected and assigned to the first subset; and a remaining segment is assigned to the second subset. The first and second subsets can separately process the time sliced segment and the remaining segment in parallel and thus avoid delay in the processing of the remaining segment. An artificial neural network (ANN) can determine a width for selecting the segment processed by the first subset; and the processing result can include a preferred width used to train the ANN.

公开(公告)号：US10942881B2

公开(公告)日：2021-03-09

申请号：US16452372

申请日：2019-06-25

Applicant: Micron Technology, Inc.

Inventor： Poorna Kale ,  Christopher Joseph Bueb

IPC: G06F13/40 ,  G06F13/16 ,  G06F13/42 ,  G06F12/10

Abstract: A solid state drive having a drive aggregator and a plurality of component solid state drives. The drive aggregator is configured to map logical addresses identified in one or more first commands into multiple logical address groups defined respectively in multiple component solid state drives. According to the one or more first commands and the logical address mapping, the drive aggregator generates multiple second commands and transmits the multiple second commands in parallel to the multiple component solid state drives to perform an operation identified by the one or more first commands.

公开(公告)号：US20240296879A1

公开(公告)日：2024-09-05

申请号：US18404587

申请日：2024-01-04

Applicant: Micron Technology, Inc.

Inventor： Christopher Joseph Bueb ,  Zheng Wang

IPC: G11C11/406 ,  G11C11/4096 ,  G11C29/52

CPC classification number: G11C11/40618 ,  G11C11/40626 ,  G11C11/4096 ,  G11C29/52

Abstract: Methods, systems, and devices for data integrity improvement programming techniques are described. A memory system may be pre-programed with data prior to assembling the memory system, where assembling the memory system may adversely affect data integrity of a portion of the data. The data integrity of the portion of the data may be improved by programming additional data to the memory system or adjusting data characteristics associated with the portion of the data. The memory system may perform a start-up procedure in which the memory system may identify an indication to perform a refresh operation. The memory system may perform a refresh operation using the additional data programmed to the memory system or using the adjusted data characteristics to improve the data integrity of the portion of the data and mitigate performance issues otherwise associated with performing the refresh operation.

公开(公告)号：US20240242752A1

公开(公告)日：2024-07-18

申请号：US18403468

申请日：2024-01-03

Applicant: Micron Technology, Inc.

Inventor： Christopher Joseph Bueb ,  Ting Luo ,  Luca Porzio ,  Gianluca Coppola ,  Ryan Laity

IPC: G11C11/406

CPC classification number: G11C11/40626 ,  G11C11/40615 ,  G11C11/40622

Abstract: Methods, systems, and devices for techniques for data refresh based on environmental conditions are described. A memory system may program data to a set of blocks, where an order in which the data be programmed to respective blocks of the set of blocks may be based on a first block ordering. The memory system may also program respective indications of respective temperatures of the programming for the respective blocks. The memory system may identify, during a start-up procedure, a flag indicating to perform a refresh operation for the set of blocks. As such, the memory system may perform during the start-up procedure, the refresh operation for the set of blocks using a second block ordering. In some examples, the second block ordering may be based on the respective indications of the respective temperatures for the set of blocks.

公开(公告)号：US11892916B2

公开(公告)日：2024-02-06

申请号：US18059321

申请日：2022-11-28

Applicant: Micron Technology, Inc.

Inventor： Poorna Kale ,  Christopher Joseph Bueb

IPC: G06F3/06 ,  G06F11/16 ,  G06F12/02 ,  G06F11/10

CPC classification number: G06F11/1612 ,  G06F3/0614 ,  G06F3/0655 ,  G06F3/0683 ,  G06F11/1092 ,  G06F12/0238

Abstract: A solid state drive having a drive aggregator and a plurality of component solid state drive, including a first component solid state drive and a second component solid state drive. The drive aggregator has at least one host interface, and a plurality of drive interfaces connected to the plurality of component solid state drives. The drive aggregator is configured to generate, in the second solid state drive, a copy of a dataset that is stored in the first component solid state drive. In response to a failure of the first component solid state drive, the drive aggregator is configured to substitute a function of the first component solid state drive with respect to the dataset with a corresponding function of the second component solid state drive, based on the copy of the dataset generated in the second component solid state drive.