公开(公告)号：US10354717B1

公开(公告)日：2019-07-16

申请号：US15976698

申请日：2018-05-10

Applicant: Micron Technology, Inc.

Inventor： Jason M. Brown ,  Vijayakrishna J. Vankayala ,  William C. Waldrop ,  Kallol Mazumder ,  Byung S. Moon ,  Ravi Kiran Kandikonda

IPC: G11C11/4076 ,  G11C11/4093 ,  G06F11/10 ,  G11C11/4096

Abstract: Aspects of the present disclosure eliminating the need for a memory device to have both a shifter that shifts input pin values from an input domain into a parity domain and another shifter that shifts a decoded command from the input domain into the parity domain. A memory device can achieve this by, when parity is being performed, shifting the input from the input pins into the parity domain prior to decoding the command. Using a multiplexer, the decoder can receive the command pin portion of the shifted input when parity checking is being performed and can receive the un-shifted command pin input when parity checking is not being performed. The decoder can use the command pin portion of the shifted input to generate shifted and decoded commands or can use the un-shifted command pin input to generate decoded commands.

公开(公告)号：US20160027706A1

公开(公告)日：2016-01-28

申请号：US14877360

申请日：2015-10-07

Applicant: Micron Technology, Inc.

Inventor： Venkatraghavan Bringivijayaraghavan ,  Jason M. Brown

IPC: H01L21/66 ,  H01L23/48

CPC classification number: H01L22/22 ,  G01R31/31717 ,  G01R31/318513 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Various embodiments comprise apparatuses and methods for testing and repairing through-substrate vias in a stack of interconnected dice. In various embodiments, an apparatus is provided that includes a number of through-substrate vias to couple to one or more devices, at least one redundant through-substrate via to allow a repair of the apparatus, and a pair of pull-up devices coupled to the through-substrate vias and the redundant through-substrate via to provide a high-data value to the first end of the respective through-substrate vias. A test register is coupled the second end of each of the through-substrate vias and the redundant through-substrate via to store a received version of the high-data value. A comparator compares the high-data value with the received version of the high-data value to test the through-substrate vias for short-circuit connections.

公开(公告)号：US20150213872A1

公开(公告)日：2015-07-30

申请号：US14168749

申请日：2014-01-30

Applicant: Micron Technology, Inc.

Inventor： Kallol Mazumder ,  Jason M. Brown ,  Derek R. May ,  Jeffrey E. Koelling ,  Roger D. Norwood

IPC: G11C11/408 ,  G11C11/406

Abstract: Apparatuses and methods for address detection are disclosed herein. An example apparatus includes an address filter and an address tracking circuit. The address filter may be configured to receive a first address and to determine whether the first address matches an address of a plurality of addresses associated with the address filter. The address tracking circuit may be coupled to the address filter and configured to store the first address responsive to a determination that the first address matches an address of the plurality of addresses associated with the address filter. The address tracking circuit may further be configured to receive a second address and to change a count associated with the first address based on the second address matching the first address. The address tracking circuit may be configured to selectively provide the first address responsive to the count.

Abstract translation: 本文公开了用于地址检测的装置和方法。 示例性设备包括地址过滤器和地址跟踪电路。 地址过滤器可以被配置为接收第一地址并且确定第一地址是否匹配与地址过滤器相关联的多个地址的地址。 地址跟踪电路可以耦合到地址过滤器并且被配置为响应于第一地址与地址过滤器相关联的多个地址的地址匹配的确定来存储第一地址。 地址跟踪电路还可以被配置为基于与第一地址匹配的第二地址来接收第二地址并改变与第一地址相关联的计数。 地址跟踪电路可以被配置为响应于计数选择性地提供第一地址。

公开(公告)号：US20140298146A1

公开(公告)日：2014-10-02

申请号：US14307249

申请日：2014-06-17

Applicant: Micron Technology, Inc.

Inventor： Jason M. Brown ,  Venkatraghavan Bringivijayaraghavan

IPC: G06F11/18

CPC classification number: G06F11/183 ,  G11C7/1006 ,  G11C7/1051 ,  G11C7/1069 ,  G11C2207/107 ,  H04L25/028 ,  H04L25/4915

Abstract: Electronic apparatus and fabrication of the electronic apparatus that includes detection of the majority of values in a plurality of data bits may be used in a variety of applications. Embodiments include application of majority bit detection to process data bits in a device for further analysis in the device based on the results of the majority bit detection. In an embodiment, such further processing in a memory device after majority bit detection may include data bit inversion prior to outputting the data from the memory device.

Abstract translation: 可以在各种应用中使用包括检测多个数据位中的大多数值的电子设备的电子设备和制造。 实施例包括应用多数位检测来处理设备中的数据位，以便基于多数位检测的结果在设备中进一步分析。 在一个实施例中，在大多数位检测之后的存储器件中的这种进一步处理可以包括在从存储器件输出数据之前的数据位反转。

公开(公告)号：US11984148B2

公开(公告)日：2024-05-14

申请号：US17470883

申请日：2021-09-09

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Penney ,  Jason M. Brown ,  Nathaniel J. Meier ,  Timothy B. Cowles ,  Jiyun Li

IPC: G11C11/406 ,  G11C11/408

CPC classification number: G11C11/40611 ,  G11C11/4085 ,  G11C11/4087

Abstract: The address of victim rows may be determined based on rows that are accessed in a memory. The victim addresses may be stored and associated with a count for every time a victim row is “victimized.” When the count for a victim row reaches a threshold, the victim row may be refreshed to preserve data stored in the row. After the victim row has been refreshed, the count may be reset. When a victim row is accessed, the count may also be reset. The counts may be adjusted for closer victim rows (e.g., +/−1) at a faster rate than counts for more distant victim rows (e.g., +/−2). This may cause closer victim rows to be refreshed at a higher rate than more distant victim rows.

公开(公告)号：US11705429B2

公开(公告)日：2023-07-18

申请号：US17013225

申请日：2020-09-04

Applicant: Micron Technology, Inc.

Inventor： Jason M. Brown ,  Vijayakrishna J. Vankayala

IPC: G11C11/00 ,  H01L25/065 ,  G11C13/00 ,  G11C29/00 ,  H10B63/00

CPC classification number: H01L25/0657 ,  G11C13/004 ,  G11C13/0069 ,  G11C29/702 ,  G11C13/003 ,  G11C13/0026 ,  G11C13/0028 ,  G11C2013/0045 ,  H01L2225/06544 ,  H10B63/84

Abstract: A device may include a first die having a first circuit and a second die having a second circuit. The die may be separated by a material layer. The material layer may include multiple through-silicon vias (TSVs) for electrically coupling the first die to the second die. A first TSV of the TSVs may electrically couple the first circuit to the second circuit and a second TSV of the TSVs may include a redundant TSV that electrically bypasses the first TSV to couple the first circuit to the second circuit if a fault is detected in the first TSV.

公开(公告)号：US20220328098A1

公开(公告)日：2022-10-13

申请号：US17853563

申请日：2022-06-29

Applicant: Micron Technology, Inc.

Inventor： Jason M. Brown ,  Vijayakrishna J. Vankayala

IPC: G11C13/00 ,  H03L7/081

Abstract: Memory devices may have a memory array and a delay locked loop (DLL) circuit that adjusts signals associated with operations to access of the memory array. The memory device may also include a controller that delays an access command to access the memory array by transmitting the access command through delay circuitry of the DLL circuit. This may cause the access command to be delayed by a first duration of time when output from the delay circuitry. Delay of the access command may align a data signal and the access command such that the access command and a system clock may cause latching of suitable data of the data signal.

公开(公告)号：US11424005B2

公开(公告)日：2022-08-23

申请号：US17060403

申请日：2020-10-01

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Daniel B. Penney ,  Jason M. Brown

IPC: G11C7/00 ,  G11C29/00 ,  G11C11/408 ,  G11C11/406

Abstract: Addresses of accessed word lines are stored. Data related to victim word lines associated with the accessed word line are also stored. The victim word lines may have data stored in relation to multiple accessed word lines. The data related to the victim word lines is adjusted when the victim word line is refreshed during a targeted refresh operation or an auto-refresh operation. The data related to the victim word lines is adjusted when the victim word line is accessed during a memory access operation.

公开(公告)号：US11158364B2

公开(公告)日：2021-10-26

申请号：US16428625

申请日：2019-05-31

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Penney ,  Jason M. Brown ,  Nathaniel J. Meier ,  Timothy B. Cowles ,  Jiyun Li

IPC: G11C7/00 ,  G11C11/406 ,  G11C11/408

Abstract: The address of victim rows may be determined based on rows that are accessed in a memory. The victim addresses may be stored and associated with a count for every time a victim row is “victimized.” When the count for a victim row reaches a threshold, the victim row may be refreshed to preserve data stored in the row. After the victim row has been refreshed, the count may be reset. When a victim row is accessed, the count may also be reset. The counts may be adjusted for closer victim rows (e.g., +/−1) at a faster rate than counts for more distant victim rows (e.g., +/−2). This may cause closer victim rows to be refreshed at a higher rate than more distant victim rows.

公开(公告)号：US11139015B2

公开(公告)日：2021-10-05

申请号：US16459520

申请日：2019-07-01

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jason M. Brown ,  Daniel B. Penney

IPC: G11C7/00 ,  G11C11/406 ,  G11C11/408

Abstract: An apparatus may include multiple memory devices. Each memory device may include multiple memory banks. Addresses of accessed word lines for a particular portion of memory and the number of times those word lines are accessed may be tracked by each memory device. When a memory device determines that an accessed word line is an aggressor word line, the memory device alerts other memory devices of the apparatus. The memory devices may then perform targeted refresh operations on victim word lines of the aggressor word line.