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公开(公告)号：US11749329B1
公开(公告)日：2023-09-05
申请号：US17749401
申请日：2022-05-20
Applicant: Micron Technology, Inc.
Inventor： Makoto Kitagawa
IPC: G11C11/22
CPC classification number: G11C11/2257 , G11C11/221 , G11C11/2255 , G11C11/2273 , G11C11/2275
Abstract: Ferroelectric memory arrays with reduced current leakage is described herein. A ferroelectric memory array may include a number of memory cells including capacitors with ferroelectric material. Providing an intermediary word line voltage to non-selected word lines that are not electrically coupled to a target memory cell during a sensing operation may reduce leakage current from an active data line electrically coupled to the target memory cell to the non-selected word lines. The intermediary word line voltage may be provided using an amplitude between an idle voltage of the data lines and zero volts. The intermediary word line voltage may be reduced closer to zero volts for performing a programming operation.
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公开(公告)号：US20230024961A1
公开(公告)日：2023-01-26
申请号：US17383090
申请日：2021-07-22
Applicant: Micron Technology, Inc.
Inventor： Makoto Kitagawa
IPC: G11C11/22 , G11C11/4091 , G11C11/4076 , G11C11/408
Abstract: Methods, systems, and devices for sense timing coordination are described. In some systems, to sense the logic states of memory cells, a memory device may generate an activation signal and route the activation signal over a signal line (e.g., a dummy word line) located at a memory array level of the memory device to one or more sense amplifiers. Based on receiving the activation signal, a sense amplifier may latch and determine the logic state of a corresponding memory cell. A first sense amplifier may sense a state of a first memory cell at a first time and a second sense amplifier may sense a state of a second memory cell at a second time in response to the same activation signal due to a propagation delay of the activation signal routed over the signal line (e.g., and corresponding to a propagation delay for activating a word line).
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公开(公告)号：US20220181338A1
公开(公告)日：2022-06-09
申请号：US17112776
申请日：2020-12-04
Applicant: Micron Technology, Inc.
Inventor： Makoto Kitagawa
IPC: H01L27/11507 , H01L27/11509 , H01L29/786 , G11C11/22
Abstract: Methods, systems, and devices for power gating in a memory device are described for using one or more memory cells as drivers for load circuits of a memory device. A group of memory cells of the memory device may represent memory cells that include a switching component and that omit a memory storage element. These memory cells may be coupled with respective plate lines that may be coupled with a voltage source having a first supply voltage. Each memory cell of the group may also be coupled with a respective digit line that may be coupled with the load circuits. Respective switching components of the group of memory cells may therefore act as drivers to apply the first supply voltage to one or more load circuits by coupling a digit line with a plate line having the first supply voltage.
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公开(公告)号：US10770143B2
公开(公告)日：2020-09-08
申请号：US16235497
申请日：2018-12-28
Applicant: Micron Technology, Inc.
Inventor： Makoto Kitagawa , Adam Johnson
Abstract: Memory systems and memory programming methods are described. According to one arrangement, a memory system includes a plurality of memory cells individually configured to have a plurality of different memory states, a plurality of bitlines coupled with the memory cells, access circuitry coupled with the bitlines and configured to apply a plurality of program signals to the bitlines to program the memory cells between the different memory states, a controller configured to control the access circuitry to provide a first program signal and a second program signal to one of the bitlines coupled with one of the memory cells to program the one memory cell from a first of the memory states to a second of the memory states, wherein the second program signal has an increased electrical characteristic compared with the first program signal, and selection circuitry configure to couple another of the bitlines which is immediately adjacent to the one bitline to a node having a first voltage which is different than a second voltage of the one bitline during the provision of the first and second program signals to the one bitline.
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公开(公告)号：US10748613B2
公开(公告)日：2020-08-18
申请号：US16176390
申请日：2018-10-31
Applicant: Micron Technology, Inc.
Inventor： Makoto Kitagawa , Kerry Tedrow
Abstract: Memory sense amplifiers and memory verification methods are described. According to one aspect, a memory sense amplifier includes a first input coupled with a memory element of a memory cell, wherein the memory element has different memory states at different moments in time, a second input configured to receive a reference signal, modification circuitry configured to provide a data signal at the first input from the memory element having a plurality of different voltages corresponding to respective ones of different memory states of the memory cell at the different moments in time, and comparison circuitry coupled with the modification circuitry and configured to compare the data signal and the reference signal at the different moments in time and to provide an output signal indicative of the memory state of the memory cell at the different moments in time as a result of the comparison to implement a plurality of verify operations of the memory states of the memory cell at the different moments in time.
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Patent Agency Ranking
公开(公告)号：US20190311767A1
公开(公告)日：2019-10-10
申请号：US16437997
申请日：2019-06-11
Applicant: Micron Technology, Inc.
Inventor： Wataru Otsuka , Takafumi Kunihiro , Tomohito Tsushima , Makoto Kitagawa , Jun Sumino , D. V. Nirmal Ramaswamy
Abstract: Memory cells, memory systems and methods are described. In one embodiment, a memory cell includes electrodes and a memory element, and a first electrically conductive structure is formed within dielectric material providing the memory element in a low resistance state as a result of a first voltage of a first polarity being applied across the electrodes. Additionally, the first electrically conductive structure is removed from the dielectric material providing the memory element in a high resistance state as a result of a second voltage of a second polarity, which is opposite to the first polarity, being applied across the electrodes. A permanent and irreversible electrically conductive structure is formed within the dielectric material providing the memory element in the low resistance state as a result of a third voltage of the second polarity and having an increased potential compared with the second voltage being applied across the electrodes.
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公开(公告)号：US20190066784A1
公开(公告)日：2019-02-28
申请号：US16174044
申请日：2018-10-29
Applicant: Micron Technology, Inc.
Inventor： Makoto Kitagawa , Yogesh Luthra
Abstract: Memory systems and memory programming methods are described. According to one aspect, a memory system includes program circuitry configured to provide a program signal to a memory cell to program the memory cell from a first memory state to a second memory state, detection circuitry configured to detect the memory cell changing from the first memory state to the second memory state during the provision of the program signal to the memory cell to program the memory cell, and wherein the program circuitry is configured to alter the program signal as a result of the detection and to provide the altered program signal to the memory cell to continue to program the memory cell from the first memory state to the second memory state.
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公开(公告)号：US20190066783A1
公开(公告)日：2019-02-28
申请号：US16176390
申请日：2018-10-31
Applicant: Micron Technology, Inc.
Inventor： Makoto Kitagawa , Kerry Tedrow
CPC classification number: G11C13/0064 , G11C7/062 , G11C11/5614 , G11C13/0011 , G11C13/004 , G11C2013/0054 , G11C2213/79
Abstract: Memory sense amplifiers and memory verification methods are described. According to one aspect, a memory sense amplifier includes a first input coupled with a memory element of a memory cell, wherein the memory element has different memory states at different moments in time, a second input configured to receive a reference signal, modification circuitry configured to provide a data signal at the first input from the memory element having a plurality of different voltages corresponding to respective ones of different memory states of the memory cell at the different moments in time, and comparison circuitry coupled with the modification circuitry and configured to compare the data signal and the reference signal at the different moments in time and to provide an output signal indicative of the memory state of the memory cell at the different moments in time as a result of the comparison to implement a plurality of verify operations of the memory states of the memory cell at the different moments in time.
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公开(公告)号：US10176868B2
公开(公告)日：2019-01-08
申请号：US14137586
申请日：2013-12-20
Applicant: Micron Technology, Inc.
Inventor： Makoto Kitagawa , Adam Johnson
Abstract: Memory systems and memory programming methods are described. According to one arrangement, a memory system includes a plurality of memory cells individually configured to have a plurality of different memory states, a plurality of bitlines coupled with the memory cells, access circuitry coupled with the bitlines and configured to apply a plurality of program signals to the bitlines to program the memory cells between the different memory states, a controller configured to control the access circuitry to provide a first program signal and a second program signal to one of the bitlines coupled with one of the memory cells to program the one memory cell from a first of the memory states to a second of the memory states, wherein the second program signal has an increased electrical characteristic compared with the first program signal, and selection circuitry configure to couple another of the bitlines which is immediately adjacent to the one bitline to a node having a first voltage which is different than a second voltage of the one bitline during the provision of the first and second program signals to the one bitline.
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公开(公告)号：US10121539B2
公开(公告)日：2018-11-06
申请号：US15495808
申请日：2017-04-24
Applicant: Micron Technology, Inc.
Inventor： Makoto Kitagawa , Yogesh Luthra
Abstract: Memory systems and memory programming methods are described. According to one aspect, a memory system includes program circuitry configured to provide a program signal to a memory cell to program the memory cell from a first memory state to a second memory state, detection circuitry configured to detect the memory cell changing from the first memory state to the second memory state during the provision of the program signal to the memory cell to program the memory cell, and wherein the program circuitry is configured to alter the program signal as a result of the detection and to provide the altered program signal to the memory cell to continue to program the memory cell from the first memory state to the second memory state.
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