公开(公告)号：US11563008B2

公开(公告)日：2023-01-24

申请号：US17194859

申请日：2021-03-08

Applicant: Micron Technology, Inc.

Inventor： Guangjun Yang ,  Vinay Nair ,  Devesh Dadhich Shreeram ,  Ashwin Panday ,  Kangle Li ,  Zhiqiang Xie ,  Silvia Borsari ,  Mohd Kamran Akhtar ,  Si-Woo Lee

IPC: H01L27/108

Abstract: Some embodiments include an integrated assembly having digit-line-contact-regions between pairs of capacitor-contact-regions. The capacitor-contact-regions are arranged with six adjacent capacitor-contact-regions in a substantially rectangular configuration. Conductive plugs are coupled with the capacitor-contact-regions. Conductive redistribution material is coupled with the conductive plugs. Upper surfaces of the conductive redistribution material are arranged in a substantially hexagonal-close-packed configuration. Digit lines are over the digit-line-contact-regions. Insulative regions are between the digit lines and the conductive plugs. The insulative regions contain voids and/or low-k dielectric material. Capacitors are coupled with the upper surfaces of the conductive redistribution material.

公开(公告)号：US20220293598A1

公开(公告)日：2022-09-15

申请号：US17197253

申请日：2021-03-10

Applicant: Micron Technology, Inc.

Inventor： Yong Mo Yang ,  Mohd Kamran Akhtar ,  Huyong Lee ,  Sangmin Hwang ,  Song Guo

IPC: H01L27/092 ,  H01L21/8238 ,  G11C7/06

Abstract: Some embodiments include an integrated assembly having a CMOS region with fins extending along a first direction, and with gating structures extending across the fins. A circuit arrangement is associated with the CMOS region and includes a pair of the gating structures spaced by an intervening region having a missing gating structure. The circuit arrangement has a first dimension along the first direction. A second region is proximate to the CMOS region. Conductive structures are associated with the second region. Some of the conductive structures are electrically coupled with the circuit arrangement. A second dimension is a distance across said some of the conductive structures along the first direction. The conductive structures and the circuit arrangement are aligned such that the second dimension is substantially the same as the first dimension. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US11239242B2

公开(公告)日：2022-02-01

申请号：US16880900

申请日：2020-05-21

Applicant: Micron Technology, Inc.

Inventor： Guangjun Yang ,  Mohd Kamran Akhtar ,  Silvia Borsari ,  Alex J. Schrinsky

IPC: H01L27/108

Abstract: Some embodiments include a method of forming an integrated assembly. A construction is formed to include a conductive structure having a top surface, and a pair of sidewall surfaces extending downwardly from the top surface. Insulative material is over the top surface, and rails are along the sidewall surfaces. The rails include sacrificial material. The sacrificial material is removed to leave openings. Sealant material is formed to extend within the openings. The sealant material has a lower dielectric constant than the insulative material. Some embodiments include an integrated assembly having a conductive structure with a top surface and a pair of opposing sidewall surfaces extending downwardly from the top surface. Insulative material is over the top surface. Voids are along the sidewall surfaces and are capped by sealant material. The sealant material has a lower dielectric constant than the insulative material.

公开(公告)号：US20220013527A1

公开(公告)日：2022-01-13

申请号：US16924995

申请日：2020-07-09

Applicant: Micron Technology, Inc.

Inventor： Yan Li ,  Song Guo ,  Mohd Kamran Akhtar ,  Alex J. Schrinsky

IPC: H01L27/108 ,  H01L21/3065

Abstract: A method of forming a microelectronic device structure comprises exposing a silicon structure to an etching chemistry at a first bias voltage of greater than about 500 V to form at least one initial trench between sidewalls of features formed in the silicon structure. The method also comprises exposing at least the sidewalls of the features to the etching chemistry at a second bias voltage of less than about 100 V to remove material from the sidewalls to expand the at least one initial trench and form at least one broader trench without substantially reducing a height of the features. Related apparatuses and electronic systems are also disclosed.

公开(公告)号：US11088147B2

公开(公告)日：2021-08-10

申请号：US16453788

申请日：2019-06-26

Applicant: Micron Technology, Inc.

Inventor： Jaydip Guha ,  Saurabh Keshav ,  Srinivas Pulugurtha ,  Mohd Kamran Akhtar ,  James B. Franek ,  Alex J. Schrinsky

IPC: H01L27/108 ,  H01L21/263 ,  H01L21/223

Abstract: Apparatus, such as electronic devices and structures thereof, include at least one doped surface of a base (e.g., semiconductor) material. A dopant of the at least one doped surface is concentrated along the surface, defining a thickness, on or in the base material, not exceeding about one atomic layer. Methods for forming the doped surfaces involve gas-phase doping exposed surfaces of the base material in situ, within a same material-removal tool used to form at least one opening defined at least partially by the base material and into which the dopant is to be introduced.

公开(公告)号：US20210233922A1

公开(公告)日：2021-07-29

申请号：US17229672

申请日：2021-04-13

Applicant: Micron Technology, Inc.

Inventor： Justin B. Dorhout ,  Kunal R. Parekh ,  Martin C. Roberts ,  Mohd Kamran Akhtar ,  Chet E. Carter ,  David Daycock

IPC: H01L27/11524 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11582 ,  H01L21/308 ,  H01L21/311 ,  H01L21/033 ,  H01L21/768 ,  H01L27/112 ,  H01L21/67 ,  H01L21/3215 ,  H01L27/11553

Abstract: Some embodiments include an integrated assembly with a semiconductor channel material having a boundary region where a more-heavily-doped region interfaces with a less-heavily-doped region. The more-heavily-doped region and the less-heavily-doped region are majority doped with a same dopant type. The integrated assembly includes a gating structure adjacent the semiconductor channel material and having a gating region and an interconnecting region of a common and continuous material. The gating region has a length extending across a segment of the more-heavily-doped region, a segment of the less-heavily-doped region, and the boundary region. The interconnecting region extends outwardly from the gating region on a side opposite the semiconductor channel region, and is narrower than the length of the gating region. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20200243537A1

公开(公告)日：2020-07-30

申请号：US16259634

申请日：2019-01-28

Applicant: Micron Technology, Inc.

Inventor： Yan Li ,  Song Guo ,  Mohd Kamran Akhtar ,  Alex J. Schrinsky

IPC: H01L27/108 ,  H01G4/08 ,  H01G4/012 ,  H01G4/008

Abstract: Methods, apparatuses, and systems related to forming a trench using a polymerizing radical material. An example method includes depositing a polymerizing radical material in a number of trenches formed over a substrate. The method further includes etching a portion of the deposited polymerizing radical material from the number of trenches. The example method further includes selectively etching into one of the number of trenches below the deposited polymerizing radical material. The one of the number of trenches is narrower than another of the number of trenches.

公开(公告)号：US20200127080A1

公开(公告)日：2020-04-23

申请号：US16167016

申请日：2018-10-22

Applicant: Micron Technology, Inc.

Inventor： Guangjun Yang ,  Mohd Kamran Akhtar

IPC: H01L49/02 ,  H01L21/3065 ,  H01L21/02 ,  H01L21/311 ,  H01L27/108 ,  H01L23/31 ,  H01L23/29

Abstract: Systems, apparatuses, and methods related to passivation material for a pillar adjacent a trench are described. An example method includes forming a passivation material on a top region of a pillar adjacent a trench of a semiconductor device and removing a first portion of the passivation material to form, on a remaining second portion of the passivation material, a surface that is coplanar with an underlying sidewall of the pillar. The example method further includes removing a portion of a substrate material at a bottom region of the trench and removing the remaining second portion of the passivation material from the top region.

公开(公告)号：US20200066729A1

公开(公告)日：2020-02-27

申请号：US16109215

申请日：2018-08-22

Applicant: Micron Technology, Inc.

Inventor： Arzum F. Simsek-Ege ,  Guangjun Yang ,  Kuo-Chen Wang ,  Mohd Kamran Akhtar ,  Katsumi Koge

IPC: H01L27/108 ,  H01L21/764 ,  G11C11/408

Abstract: A semiconductor device comprises semiconductive pillars; digit lines laterally between the semiconductive pillars; nitride caps vertically overlying the digit lines; nitride structures overlying surfaces of the nitride caps; redistribution material structures comprising upper portions overlying upper surfaces of the nitride caps and the nitride structures, and lower portions overlying upper surfaces of the semiconductive pillars; a low-K dielectric material laterally between the digit lines and the semiconductive pillars; air gaps laterally between the low-K dielectric material and the semiconductive pillars, and having upper boundaries below the upper surfaces of the nitride caps; and a nitride dielectric material laterally between the air gaps and the semiconductive pillars. Memory devices, electronic systems, and method of forming a semiconductor device are also described.

公开(公告)号：US20200058663A1

公开(公告)日：2020-02-20

申请号：US16663068

申请日：2019-10-24

Applicant: Micron Technology, Inc.

Inventor： Justin B. Dorhout ,  Kunal R. Parekh ,  Martin C. Roberts ,  Mohd Kamran Akhtar ,  Chet E. Carter ,  David Daycock

IPC: H01L27/11524 ,  H01L27/11553 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/11551

Abstract: Some embodiments include an integrated assembly with a semiconductor channel material having a boundary region where a more-heavily-doped region interfaces with a less-heavily-doped region. The more-heavily-doped region and the less-heavily-doped region have the same majority carriers. The integrated assembly includes a gating structure adjacent the semiconductor channel material and having a gating region and an interconnecting region of a common and continuous material. The gating region has a length extending along a segment of the more-heavily-doped region, a segment of the less-heavily-doped region, and the boundary region. The interconnecting region extends laterally outward from the gating region on a side opposite the semiconductor channel region, and is narrower than the length of the gating region. Some embodiments include methods of forming integrated assemblies.