公开(公告)号：US20240341079A1

公开(公告)日：2024-10-10

申请号：US18600324

申请日：2024-03-08

Applicant: Micron Technology, Inc.

Inventor： Babak Tahmouresilerd ,  Ramaswamy Ishwar Venkatanarayanan ,  Don Koun Lee ,  Purnima Narayanan ,  Sanjeev Sapra

IPC: H10B12/00

CPC classification number: H10B12/053 ,  H10B12/34

Abstract: Methods, systems, and devices for wordline recess formation and resulting structures are described. In some instances, aspects of a memory device may be formed using a wet etching process. For example, a wet etching process may be used to remove (e.g., etch) one or more materials (e.g., nitrides) when forming wordlines. The wet etching process may include depositing a first resist material and a second resist material to selectively remove (e.g., etch) different portions of the nitride material. Such processes may result in gate oxides of the memory device being relatively uniform in shape.

公开(公告)号：US20230354585A1

公开(公告)日：2023-11-02

申请号：US17731895

申请日：2022-04-28

Applicant: Micron Technology, Inc.

Inventor： Albert P. Chan ,  Sanjeev Sapra ,  Vivek Yadav ,  Yen Ting Lin ,  Devesh Dadhich Shreeram

IPC: H01L27/108

CPC classification number: H01L27/10885 ,  H01L27/10814

Abstract: Methods, apparatuses, and systems related to a digit line and cell contact are described. An example apparatus includes a semiconductor structure comprising a first layer comprising a first material on sidewalls of a plurality of patterned material. The apparatus further includes a second layer comprising a nitride material on sidewalls of the first layer. The apparatus further includes a third layer comprising the first material on sidewalls of the second layer. The apparatus further includes a base area, to provide digit line and cell contact isolation for the semiconductor structure. The apparatus further includes an active area, adjacent to the base area, that is adjacent to the semiconductor structure.

公开(公告)号：US11114443B2

公开(公告)日：2021-09-07

申请号：US16555565

申请日：2019-08-29

Applicant: Micron Technology, Inc.

Inventor： Vivek Yadav ,  Fatma Arzum Simsek-Ege ,  Sanjeev Sapra ,  Thomas A. Figura ,  Kangle Li

IPC: H01L27/108 ,  H01L29/78 ,  H01L21/67 ,  H01L21/762

Abstract: Systems, apparatuses, and methods related to semiconductor structure formation are described. An example method may include patterning a working surface of a semiconductor wafer. The method may further include performing a vapor etch on a first dielectric material at the working surface to recess the first dielectric material to a first intended depth of an opening relative to the working surface and to expose a second dielectric material on a sidewall of the opening. The method may further include performing a wet etch on the second dielectric material to recess the second dielectric material to the intended depth.

公开(公告)号：US20210159069A1

公开(公告)日：2021-05-27

申请号：US17168393

申请日：2021-02-05

Applicant: Micron Technology, Inc.

Inventor： Michael T. Andreas ,  Jerome A. Imonigie ,  Prashant Raghu ,  Sanjeev Sapra ,  Ian K. McDaniel

IPC: H01L21/02 ,  B81C1/00

Abstract: In an example, a wet cleaning process is performed to clean a structure having features and openings between the features while preventing drying of the structure. After performing the wet cleaning process, a polymer solution is deposited in the openings while continuing to prevent any drying of the structure. A sacrificial polymer material is formed in the openings from the polymer solution. The structure may be used in semiconductor devices, such as integrated circuits, memory devices, MEMS, among others.

公开(公告)号：US11011523B2

公开(公告)日：2021-05-18

申请号：US16258933

申请日：2019-01-28

Applicant: Micron Technology, Inc.

Inventor： Devesh Dadhich Shreeram ,  Diem Thy N. Tran ,  Sanjeev Sapra

IPC: H01L27/108 ,  H01L27/105

Abstract: Methods, apparatuses, and systems related to forming a capacitor column using a sacrificial material are described. An example method includes patterning a surface of a semiconductor substrate having: a first silicate material over the substrate, a first nitride material over the first silicate material, a sacrificial material over the first nitride material, a second silicate material over the sacrificial material, and a second nitride material over the second silicate material. The method further includes forming a column of capacitor material in an opening through the first silicate material, the first nitride material, the sacrificial material, the second silicate material, and the second nitride material. The method further includes removing the sacrificial material.

公开(公告)号：US10978306B2

公开(公告)日：2021-04-13

申请号：US16369797

申请日：2019-03-29

Applicant: Micron Technology, Inc.

Inventor： Jerome A. Imonigie ,  Adriel Jebin Jacob Jebaraj ,  Brian J. Kerley ,  Sanjeev Sapra ,  Ashwin Panday

IPC: H01L21/306 ,  H01L49/02 ,  H01L21/311 ,  H01L27/108 ,  H01L21/3213 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/02 ,  H01L21/302

Abstract: Methods, apparatuses, and systems related to forming a recess in a semiconductor structure are described. An example method includes etching the semiconductor structure using an elevated temperature dilution of acid and water. The method further includes etching the semiconductor structure using a room temperature wet etch of acid and water and a surface modification chemistry.

公开(公告)号：US20210066307A1

公开(公告)日：2021-03-04

申请号：US16555565

申请日：2019-08-29

Applicant: Micron Technology, Inc.

Inventor： Vivek Yadav ,  Fatma Arzum Simsek-Ege ,  Sanjeev Sapra ,  Thomas A. Figura ,  Kangle Li

IPC: H01L27/108

Abstract: Systems, apparatuses, and methods related to semiconductor structure formation are described. An example method may include patterning a working surface of a semiconductor wafer. The method may further include performing a vapor etch on a first dielectric material at the working surface to recess the first dielectric material to a first intended depth of an opening relative to the working surface and to expose a second dielectric material on a sidewall of the opening. The method may further include performing a wet etch on the second dielectric material to recess the second dielectric material to the intended depth.

公开(公告)号：US20210057266A1

公开(公告)日：2021-02-25

申请号：US16549594

申请日：2019-08-23

Applicant: Micron Technology, Inc.

Inventor： Vivek Yadav ,  Shen Hu ,  Kangle Li ,  Sanjeev Sapra

IPC: H01L21/762 ,  H01L27/108 ,  H01L21/02 ,  H01L21/67

Abstract: An example method includes patterning a working surface of a semiconductor wafer. The example method includes performing a first deposition of a dielectric material in high aspect ratio trenches. The example method further includes performing a high pressure, high temperature vapor etch to recess the dielectric material in the trenches and performing a second deposition of the dielectric material to continue filling the trenches.

公开(公告)号：US10930499B2

公开(公告)日：2021-02-23

申请号：US16379085

申请日：2019-04-09

Applicant: Micron Technology, Inc.

Inventor： Nicholas R. Tapias ,  Sanjeev Sapra ,  Anish A. Khandekar ,  Shen Hu

IPC: H01L21/02 ,  H01L21/762 ,  H01L21/8238

Abstract: Methods, apparatuses, and systems related to semiconductor structure formation are described. An example method includes forming an opening through silicon (Si) material, formed over a semiconductor substrate, to a first depth to form pillars of Si material. The example method further includes depositing an isolation material within the opening to fill the opening between the Si pillars. The example method further includes removing a portion of the isolation material from between the pillars to a second depth to create a second opening between the pillars and defining inner sidewalls between the pillars. The example method further includes depositing an enhancer material over a top surface of the pillars and along the inner sidewalls of the pillars down to a top portion of the isolation material.

公开(公告)号：US20200328080A1

公开(公告)日：2020-10-15

申请号：US16379085

申请日：2019-04-09

Applicant: Micron Technology, Inc.

Inventor： Nicholas R. Tapias ,  Sanjeev Sapra ,  Anish A. Khandekar ,  Shen Hu

IPC: H01L21/02 ,  H01L21/762

Abstract: Methods, apparatuses, and systems related to semiconductor structure formation are described. An example method includes forming an opening through silicon (Si) material, formed over a semiconductor substrate, to a first depth to form pillars of Si material. The example method further includes depositing an isolation material within the opening to fill the opening between the Si pillars. The example method further includes removing a portion of the isolation material from between the pillars to a second depth to create a second opening between the pillars and defining inner sidewalls between the pillars. The example method further includes depositing an enhancer material over a top surface of the pillars and along the inner sidewalls of the pillars down to a top portion of the isolation material.