-
公开(公告)号：US20220343990A1
公开(公告)日：2022-10-27
申请号：US17302215
申请日：2021-04-27
Applicant: Micron Technology, Inc.
Inventor： Seungjune Jeon , Tingjun Xie
Abstract: A corresponding value of a data state metric associated with each of a value of a plurality of values of a memory access operation parameter used in one or more memory access operation is measured. An optimal metric value based on the measured values of the predetermined data state metric is determined. An optimal value of the memory access operation parameter from the plurality of values of the memory access operation parameter is selected.
-
公开(公告)号：US20220058087A1
公开(公告)日：2022-02-24
申请号：US16997500
申请日：2020-08-19
Applicant: Micron Technology, Inc.
Inventor： Seungjune Jeon
IPC: G06F11/14
Abstract: An apparatus includes an error read flow component resident on a memory sub-system. The error read flow component can cause performance of a plurality of read recovery operations on a group of memory cells that are programmed or read together, or both. The error read flow component can determine whether a particular read recovery operation invoking the group of memory cells was successful. The error read flow component can further cause a counter corresponding to each of the plurality of read recovery operations to be incremented in response to a determination that the particular read recovery operation invoking the group of memory cells was successful.
-
公开(公告)号：US10950315B1
公开(公告)日：2021-03-16
申请号：US16715639
申请日：2019-12-16
Applicant: Micron Technology, Inc.
Inventor： Seungjune Jeon , Zhenming Zhou , Zhenlei Shen
Abstract: A request to read data at the memory device is received. A first read operation is performed to read the data at the memory device using a first read threshold voltage. The data read at the memory device using the first read threshold voltage is determined to be associated with a first unsuccessful correction of an error. Responsive to determining that the data read at the memory device using the first read threshold voltage is associated with the first unsuccessful correction of the error, a second read threshold voltage is stored at a register to replace a preread threshold voltage previously stored at the register that is associated with the memory device. The first preread threshold voltage was previously used to perform a preread operation at the memory device. A second read operation to read the data at the memory device is performed using the second read threshold voltage.
-
公开(公告)号：US20250004647A1
公开(公告)日：2025-01-02
申请号：US18677578
申请日：2024-05-29
Applicant: Micron Technology, Inc.
Inventor： Ying Yu Tai , Jun Wan , Seungjune Jeon , Zhenming Zhou , Jiangli Zhu
IPC: G06F3/06
Abstract: A processing device analyzes one or more property and capability characteristics of a plurality of memory devices produced in a development process executed by a memory device development system and identifies respective subsets of the plurality of memory devices having property and capability characteristics that meet respective standards associated with a plurality of different use cases. The processing device further allocates the respective subsets to groups of memory devices corresponding to the different use cases.
-
公开(公告)号：US12164779B2
公开(公告)日：2024-12-10
申请号：US18103133
申请日：2023-01-30
Applicant: Micron Technology, Inc.
Inventor： Zhenming Zhou , Seungjune Jeon , Zhenlei Shen
Abstract: Systems and methods are disclosed including a processing device operatively coupled to memory device. The processing device performs operations comprising responsive to receiving a memory access command, determining a portion of the memory device that is referenced by a logical address specified by the memory access command; determining an endurance factor associated with the portion; and modifying, based on a value derived from the endurance factor, a media management metric associated with the portion of the memory device.
-
Patent Agency Ranking
公开(公告)号：US12026042B2
公开(公告)日：2024-07-02
申请号：US17858731
申请日：2022-07-06
Applicant: Micron Technology, Inc.
Inventor： Charles See Yeung Kwong , Seungjune Jeon , Wei Wang , Zhenming Zhou
CPC classification number: G06F11/076 , G06F11/008 , G06F11/073 , G06F2201/81 , G06F2212/7211
Abstract: A set of blocks of a memory device comprising a plurality of dies is identified. A block within the set of blocks is identified. The identified block is associated with a capability metric that reflects a projected reliability of the die on which the block resides. Responsive to determining that the capability metric satisfies a condition, a cycle threshold associated with the die is identified. Responsive to determining that a cycle count value derived from a program/erase cycle counter associated with the die matches the cycle threshold, the set of blocks is updated by excluding the block from the set of blocks. A program operation is performed with respect to the updated set of blocks.
-
37.发明公开公开(公告)号：US20240062839A1
公开(公告)日：2024-02-22
申请号：US17892437
申请日：2022-08-22
Applicant: Micron Technology, Inc.
Inventor： Wei Wang , Seungjune Jeon , Yang Liu , Charles See Yeung Kwong
CPC classification number: G11C16/3431 , G11C16/0483
Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations comprising performing a data integrity check on a set of memory cells of a source management unit of the memory device to obtain a data integrity metric value; determining whether the data integrity metric value satisfies a first threshold; responsive to determining that the data integrity metric value fails to satisfy the first threshold, determining whether the data integrity metric value satisfies a second threshold that is lower than the first threshold; responsive to determining that the data integrity metric value satisfies the second threshold, causing the memory device to copy data from the source management unit to a destination set of pages of the memory device; and performing a subsequent data integrity check on one or more invalid pages of the source management unit.
-
38.发明授权公开(公告)号：US11756604B2
公开(公告)日：2023-09-12
申请号：US17946612
申请日：2022-09-16
Applicant: Micron Technology, Inc.
Inventor： Charles See Yeung Kwong , Seungjune Jeon
IPC: G11C11/406 , G11C29/42 , G11C11/4096
CPC classification number: G11C11/40622 , G11C11/4096 , G11C11/40615 , G11C29/42
Abstract: A memory access operation performed on a first memory unit of a memory device is detected. A counter associated with the first memory unit is modified. It is determined that the counter satisfies a threshold criterion, wherein the threshold criterion is based on a random or pseudo-random number within a margin of an average number of memory access operations. A refresh operation is performed on a second memory unit.
-
39.发明授权公开(公告)号：US11709622B2
公开(公告)日：2023-07-25
申请号：US17489405
申请日：2021-09-29
Applicant: Micron Technology, Inc.
Inventor： Fangfang Zhu , Juane Li , Seungjune Jeon , Jiangli Zhu , Ying Tai
CPC classification number: G06F3/0655 , G06F3/0604 , G06F3/0679
Abstract: Systems and methods are disclosed including a memory device and a processing device, operatively coupled with the memory device, to perform operations comprising: receiving a write data request to store write data to the memory device; determining a physical block address associated with the write data request; performing a bitwise operation on each bit of the physical block address to generate a seed value; generating an output sequence based on the seed value; performing another bitwise operation on the output sequence and the write data to generate a randomized sequence; and storing, on the memory device, the randomized sequence.
-
公开(公告)号：US11599272B2
公开(公告)日：2023-03-07
申请号：US17348226
申请日：2021-06-15
Applicant: Micron Technology, Inc.
Inventor： Zhenming Zhou , Seungjune Jeon , Zhenlei Shen
Abstract: Systems and methods are disclosed including a processing device operatively coupled to memory device. The processing device performs operations comprising receiving a memory access command specifying a logical address; determining a physical address associated with the logical address; determining a portion of the memory device that is referenced by the physical address; determine an endurance factor associated with the portion; and increasing, by a value derived from the endurance factor, a media management metric associated with a management unit of the memory device, wherein the management unit is referenced by the physical address.
-
-
-
-
-
-
-
-
-
Search Results
59
records
(took 0.021 seconds)
