公开(公告)号：US11199999B2

公开(公告)日：2021-12-14

申请号：US16777766

申请日：2020-01-30

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Ying Yu Tai ,  Jiangli Zhu

IPC: G06F3/06

Abstract: A processing device, operatively coupled with a memory device, is configured to receive a write request identifying data to be stored in a segment of the memory device. The processing device determines a write-to-write (W2W) time interval for the segment and determines whether the W2W time interval falls within a first W2W time interval range, the first W2W time interval range corresponds to a first pre-read voltage level. Responsive to the W2W time interval for the segment falling within the first W2W interval range, the processing device performs a pre-read operation on the segment using the first pre-read voltage level. The processing device identifies a subset of the data to be stored in the segment comprising bits of data that are different than corresponding bits of the data stored in the segment. The processing device further performs a write operation to store the subset of the data in the segment.

公开(公告)号：US20210271421A1

公开(公告)日：2021-09-02

申请号：US17303169

申请日：2021-05-21

Applicant: Micron Technology, Inc.

Inventor： Jiangli Zhu ,  Wei Wang ,  Ying Yu Tai ,  Jason Duong ,  Chih-Kuo Kao

IPC: G06F3/06

Abstract: A processing device in a memory system determines that a number of commands from an active queue that have been executed on a memory device does not satisfy an executed transaction threshold criterion, that a number of pending commands in an inactive queue satisfies a first promotion threshold criterion, and that a number of pending commands in the active queue does not satisfy a second promotion threshold criterion. In response, the processing device switches an execution grant from the active queue to the inactive queue.

公开(公告)号：US20210089218A1

公开(公告)日：2021-03-25

申请号：US17114380

申请日：2020-12-07

Applicant: Micron Technology, Inc.

Inventor： Fangfang Zhu ,  Jiangli Zhu ,  Ning Chen ,  Ying Yu Tai

IPC: G06F3/06 ,  G06F12/10

Abstract: Data is copied, to a first group of data blocks in a first plurality of groups of unmapped data blocks, from a second group of data blocks in a second plurality of groups of mapped data blocks. Upon copying data to the first group of data blocks from the second group of data blocks, the first group of data blocks is included in the second plurality of groups of mapped data blocks. Upon including the first group of data blocks in the second plurality of groups of mapped data blocks, a wear leveling operation is performed on the first group of data blocks, wherein performing the wear leveling operation comprises determining a base address of the first group of data blocks, the base address indicating a location at which the first group of data blocks begins. A request to access subsequent data at a logical address associated with a data block included in the first group of data blocks is received. A physical address based on the base address of the first group of data blocks and the logical address is determined. The subsequent data is accessed at the first group of data blocks based on the physical address.

公开(公告)号：US20210027812A1

公开(公告)日：2021-01-28

申请号：US16949036

申请日：2020-10-09

Applicant: Micron Technology, Inc.

Inventor： Edward McGlaughlin ,  Ying Yu Tai ,  Samir Mittal

IPC: G11C5/14 ,  G11C13/00 ,  G11C11/4074 ,  G06F3/06

Abstract: A processing device determines a subset of a plurality of blocks from a volatile memory device of a memory sub-system, retrieves the subset of the plurality of blocks from the volatile memory device, and writes the subset of the plurality of blocks to a non-volatile cross point array memory device of the memory sub-system using a first type of write operation. The processing device further receives an indication of a power loss in the memory sub-system, and responsive to receiving the indication of the power loss, writes a remainder of the plurality of blocks to the non-volatile cross point array memory device using a second type of write operation.

公开(公告)号：US20210019450A1

公开(公告)日：2021-01-21

申请号：US16913748

申请日：2020-06-26

Applicant: Micron Technology, Inc.

Inventor： Juane Li ,  Jiangli Zhu ,  Ying Yu Tai

IPC: G06F21/79 ,  G06F21/60 ,  H04L9/08 ,  G11C29/42 ,  G11C29/44

Abstract: Methods, systems, and devices for cryptographic key management are described. A memory device can issue, by a firmware component, a command to generate a first cryptographic key for encrypting or decrypting user data stored on a memory device. The memory device can generate, by a hardware component, the first cryptographic key based on the command. The memory device can encrypt, by the hardware component, the first cryptographic key using a second cryptographic key and an initialization vector. The memory device can store the encrypted first cryptographic key in a nonvolatile memory device separate from the hardware component.

公开(公告)号：US20210019217A1

公开(公告)日：2021-01-21

申请号：US16784966

申请日：2020-02-07

Applicant: Micron Technology, Inc.

Inventor： Jiangli Zhu ,  Ying Yu Tai ,  Fangfang Zhu ,  Wei Wang

IPC: G06F11/07 ,  G06F11/10 ,  G06F11/14 ,  G06F11/30 ,  G06F9/54 ,  G06F9/30

Abstract: In an embodiment, a system includes a plurality of memory components and a processing device that is operatively coupled with the plurality of memory components. The processing device includes a host interface, an access management component, a media management component (MMC), and an MMC-restart manager that is configured to perform operations including detecting a triggering event for restarting the MMC, and responsively performing MMC-restart operations that include suspending operation of the access management component; determining whether the MMC is operating, and if so then suspending operation of the MMC; resetting the MMC; resuming operation of the MMC; and resuming operation of the access management component.

公开(公告)号：US20210019058A1

公开(公告)日：2021-01-21

申请号：US16874389

申请日：2020-05-14

Applicant: Micron Technology, Inc.

Inventor： Fangfang Zhu ,  Ying Yu Tai ,  Ning Chen ,  Jiangli Zhu ,  Alex Tang

IPC: G06F3/06

Abstract: Embodiments include methods, systems, devices, instructions, and media for limiting hot-cold swap wear leveling in memory devices. In one embodiment, wear metric values are stored and monitored using multiple wear leveling criteria. The multiple wear leveling criteria include a hot-cold swap wear leveling criteria, which may make use of a write count offset value. Based on a first wear metric value of a first management group and a second wear metric value of a second management group, the first management group and the second management group are selected for a wear leveling swap operation. The wear leveling swap operation is performed with a whole management group read operation of the first management group to read a set of data, and a whole management group write operation to write the set of data to the second management group.

公开(公告)号：US20200250033A1

公开(公告)日：2020-08-06

申请号：US16265690

申请日：2019-02-01

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Tingjun Xie ,  Ying Yu Tai ,  Jiangli Zhu

IPC: G06F11/10 ,  G06F12/02 ,  H03M13/13

Abstract: Data to be stored at a memory sub-system can be received from a host system. A portion of the host data that includes user data and another portion of the host data that includes system metadata can be determined. A mapping for a data structure can be received that identifies locations of the data structure that are fixed with respect to an encoding operation and locations of the data structure that are not fixed with respect to the encoding operation. The data structure can be generated for the user data and system metadata based on the mapping, and an encoding operation can be performed on the data structure to generate a codeword.

公开(公告)号：US10672486B2

公开(公告)日：2020-06-02

申请号：US16107878

申请日：2018-08-21

Applicant: Micron Technology, Inc.

Inventor： Fangfang Zhu ,  Jiangli Zhu ,  Ying Yu Tai

IPC: G11C16/34 ,  G11C13/00 ,  G11C29/52 ,  G11C11/406

Abstract: One or more write operations are performed on a memory component. A determination is made as to whether a number of the plurality of write operations performed on the memory component since performance of a refresh operation on the memory component exceeds a threshold value. In response to determining that the number of write operations performed on the memory component exceeds the threshold value, a memory cell of the memory component is identified based on the plurality of write operations. Data stored at memory cells of the memory component that are proximate to the identified memory cell is refreshed.

公开(公告)号：US20200089429A1

公开(公告)日：2020-03-19

申请号：US16132096

申请日：2018-09-14

Applicant: Micron Technology, Inc.

Inventor： Jiangli Zhu ,  Cheng Yuan Wu ,  Ying Yu Tai

IPC: G06F3/06

Abstract: A host operation to be performed can be received. Sub-operations that are associated with the received host operation can be determined. A memory component of multiple memory components can be identified for each sub-operation. Furthermore, each sub-operation can be transmitted to a media sequencer component that is associated with a respective memory component of the memory components.