中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

51 records (took 0.019 seconds)

    Assemblies Which Include Ruthenium-Containing Conductive Gates
    34.
    发明申请
    Assemblies Which Include Ruthenium-Containing Conductive Gates 有权

    公开(公告)号：US20210217863A1

    公开(公告)日：2021-07-15

    申请号：US17194971

    申请日：2021-03-08

    Applicant: Micron Technology, Inc.

    Inventor： Ramanathan Gandhi

    IPC: H01L29/423 ,  H01L29/49 ,  H01L27/11565 ,  H01L27/11582

    Abstract: Some embodiments include a memory cell having a conductive gate comprising ruthenium. A charge-blocking region is adjacent the conductive gate, a charge-storage region is adjacent the charge-blocking region, a tunneling material is adjacent the charge-storage region, and a channel material is adjacent the tunneling material. Some embodiments include an assembly having a vertical stack of alternating insulative levels and wordline levels. The wordline levels contain conductive wordline material which includes ruthenium. Semiconductor material extends through the stack as a channel structure. Charge-storage regions are between the conductive wordline material and the channel structure. Charge-blocking regions are between the charge-storage regions and the conductive wordline material. Some embodiments include methods of forming integrated assemblies.

    Assemblies which include ruthenium-containing conductive gates
    35.
    发明授权
    Assemblies which include ruthenium-containing conductive gates 有权

    公开(公告)号：US10964793B2

    公开(公告)日：2021-03-30

    申请号：US16383964

    申请日：2019-04-15

    Applicant: Micron Technology, Inc.

    Inventor： Ramanathan Gandhi

    IPC: H01L29/423 ,  H01L29/49 ,  H01L27/11565 ,  H01L27/11582

    Abstract: Some embodiments include a memory cell having a conductive gate comprising ruthenium. A charge-blocking region is adjacent the conductive gate, a charge-storage region is adjacent the charge-blocking region, a tunneling material is adjacent the charge-storage region, and a channel material is adjacent the tunneling material. Some embodiments include an assembly having a vertical stack of alternating insulative levels and wordline levels. The wordline levels contain conductive wordline material which includes ruthenium. Semiconductor material extends through the stack as a channel structure. Charge-storage regions are between the conductive wordline material and the channel structure. Charge-blocking regions are between the charge-storage regions and the conductive wordline material. Some embodiments include methods of forming integrated assemblies.

    Ferroelectric Devices and Methods of Forming Ferroelectric Devices
    36.
    发明申请
    Ferroelectric Devices and Methods of Forming Ferroelectric Devices 审中-公开

    公开(公告)号：US20200227423A1

    公开(公告)日：2020-07-16

    申请号：US16834666

    申请日：2020-03-30

    Applicant: Micron Technology, Inc.

    Inventor： Ashonita A. Chavan ,  Ramanathan Gandhi ,  Beth R. Cook ,  Durai Vishak Nirmal Ramaswamy

    IPC: H01L27/11507 ,  H01L21/28 ,  H01L29/51 ,  H01L29/78 ,  H01L29/66 ,  H01L27/1159 ,  H01L49/02

    Abstract: Some embodiments include a ferroelectric device comprising ferroelectric material adjacent an electrode. The device includes a semiconductor material-containing region along a surface of the ferroelectric material nearest the electrode. The semiconductor material-containing region has a higher concentration of semiconductor material than a remainder of the ferroelectric material. The device may be, for example, a transistor or a capacitor. The device may be incorporated into a memory array. Some embodiments include a method of forming a ferroelectric capacitor. An oxide-containing ferroelectric material is formed over a first electrode. A second electrode is formed over the oxide-containing ferroelectric material. A semiconductor material-enriched portion of the oxide-containing ferroelectric material is formed adjacent the second electrode.

    Ferroelectric Devices and Methods of Forming Ferroelectric Devices
    37.
    发明申请
    Ferroelectric Devices and Methods of Forming Ferroelectric Devices 审中-公开

    公开(公告)号：US20170345831A1

    公开(公告)日：2017-11-30

    申请号：US15164749

    申请日：2016-05-25

    Applicant: Micron Technology, Inc.

    Inventor： Ashonita A. Chavan ,  Ramanathan Gandhi ,  Beth R. Cook ,  Durai Vishak Nirmal Ramaswamy

    IPC: H01L27/11507 ,  H01L49/02

    Abstract: Some embodiments include a ferroelectric device comprising ferroelectric material adjacent an electrode. The device includes a semiconductor material-containing region along a surface of the ferroelectric material nearest the electrode. The semiconductor material-containing region has a higher concentration of semiconductor material than a remainder of the ferroelectric material. The device may be, for example, a transistor or a capacitor. The device may be incorporated into a memory array. Some embodiments include a method of forming a ferroelectric capacitor. An oxide-containing ferroelectric material is formed over a first electrode. A second electrode is formed over the oxide-containing ferroelectric material. A semiconductor material-enriched portion of the oxide-containing ferroelectric material is formed adjacent the second electrode.

    Memory devices including oxide semiconductor
    39.
    发明授权
    Memory devices including oxide semiconductor 有权

    公开(公告)号：US12199183B2

    公开(公告)日：2025-01-14

    申请号：US17822420

    申请日：2022-08-25

    Applicant: Micron Technology, Inc.

    Inventor： Scott E. Sills ,  Ramanathan Gandhi ,  Durai Vishak Nirmal Ramaswamy

    IPC: H01L29/786 ,  H01L29/66 ,  H10B63/00

    Abstract: A method of forming a device comprises forming dielectric structures over other dielectric structures overlying conductive contact structures, the dielectric structures separated from one another by trenches and laterally extending orthogonal to the other dielectric structures and the conductive contact structures. Conductive gate structures are formed on exposed side surfaces of the dielectric structures within the trenches. Dielectric oxide structures are formed on exposed side surfaces of the conductive gate structures within the trenches. Exposed portions of the other dielectric structures are removed to form isolation structures. Semiconductive pillars are formed on exposed side surfaces of the dielectric oxide structures and the isolation structures within the trenches. The semiconductive pillars are in electrical contact with the conductive contact structures. Additional conductive contact structures are formed on upper surfaces of the semiconductive pillars. A device, a memory device, and an electronic system are also described.

Patent Agency Ranking