公开(公告)号：US20240265991A1

公开(公告)日：2024-08-08

申请号：US18640651

申请日：2024-04-19

Applicant: Micron Technology, Inc.

Inventor： Scott E. Schaefer

IPC: G11C29/44 ,  G11C29/12 ,  G11C29/18 ,  G11C29/42

CPC classification number: G11C29/4401 ,  G11C29/1201 ,  G11C29/18 ,  G11C29/42 ,  G11C2029/1806

Abstract: Methods, systems, and devices for bit retiring to mitigate bit errors are described. A memory device may retrieve a set of bits from a first row of an address space and may determine that the set of bits includes one or more errors. The memory device may remap at least a portion of the first row from a first row index to a second row index, where the second row index, before the remapping, corresponds to a second row within the address space addressable by the host device. Additionally or alternatively, the memory device may receive a first command to access a first logical address of a memory array that is associated with a first row index. The memory device may determine that the first row includes one or more errors and may transmit a signal indicating that the first row includes the one or more errors.

公开(公告)号：US12046316B2

公开(公告)日：2024-07-23

申请号：US17502982

申请日：2021-10-15

Applicant: Micron Technology, Inc.

Inventor： Scott E. Schaefer ,  Aaron P. Boehm

IPC: G11C8/18 ,  G11C29/12 ,  G11C29/14 ,  G11C29/42

CPC classification number: G11C29/42 ,  G11C8/18 ,  G11C29/12005 ,  G11C29/14 ,  G11C2029/1208

Abstract: Methods, systems, and devices for techniques for detecting a state of a bus are described. A memory device may fail to receive or decode (e.g., successfully receive or successfully decode) an access command transmitted to the memory device via a bus. The bus may enter or remain in an idle state which may cause indeterminate signals to develop on the idle bus. A host device may obtain the indeterminate signals from the idle bus and determine that the indeterminate signals include an error based on a signal that develops on a control line of the idle bus. The signal may be associated with a control signal that indicates errors in a data signal when the control signal has a first voltage, and the control line may be configured to have the first voltage when the bus is idle.

公开(公告)号：US11984180B2

公开(公告)日：2024-05-14

申请号：US17807314

申请日：2022-06-16

Applicant: Micron Technology, Inc.

Inventor： Scott E. Schaefer

IPC: G11C29/00 ,  G11C29/10 ,  G11C29/42 ,  G11C29/44 ,  G11C29/46

CPC classification number: G11C29/42 ,  G11C29/10 ,  G11C29/4401 ,  G11C29/46

Abstract: Implementations described herein relate to enabling or disabling on-die error-correcting code for a memory built-in self-test. A memory device may read one or more bits, associated with a memory built-in self-test, that are stored in a mode register of the memory device. The memory device may identify, based on the one or more bits, whether the memory built-in self-test is to be performed with on-die error-correcting code (ECC) disabled or with on-die ECC enabled. The memory device may perform the memory built-in self-test, and selectively test for one or more single-bit errors, based on identifying whether the memory built-in self-test is to be performed with the on-die ECC disabled or with the on-die ECC enabled.

公开(公告)号：US11977772B2

公开(公告)日：2024-05-07

申请号：US17464333

申请日：2021-09-01

Applicant: Micron Technology, Inc.

Inventor： Aaron P. Boehm ,  Todd Jackson Plum ,  Scott D. Van De Graaff ,  Scott E. Schaefer ,  Mark D. Ingram

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0653 ,  G06F3/0679

Abstract: Methods, systems, and devices for temperature monitoring for memory devices are described for monitoring one or more temperature ranges experienced by a memory device. The memory device may include monitoring circuitry or logic that may identify one or more durations of operating the memory device within the one or more temperature ranges. The memory device may store an indication of the one or more durations, or an indication of information associated with the one or more durations. The indication may be accessed a host device associated with the memory device or may be transmitted by the memory device to the host device. The host device may use information included in the indication to perform an operation associated with the memory device.

公开(公告)号：US11880291B2

公开(公告)日：2024-01-23

申请号：US17354690

申请日：2021-06-22

Applicant: Micron Technology, Inc.

Inventor： Todd Jackson Plum ,  Scott D. Van De Graaff ,  Scott E. Schaefer ,  Aaron P Boehm ,  Mark D. Ingram

IPC: G06F11/00 ,  G06F11/30 ,  G06F11/14 ,  G06F11/07

CPC classification number: G06F11/3037 ,  G06F11/0772 ,  G06F11/1417 ,  G06F11/3075

Abstract: Methods, systems, and devices for monitoring and reporting a status of a memory device are described. A memory device may include monitoring circuitry that may be configured to monitor health and wear information for the memory device. A host device may write to a dedicated register of the memory device, to configure the memory device with health status information reporting parameters. The memory device may monitor and report the health status information of the memory device based on the received reporting configuration or based on a default configuration, and may write one or more values indicative of the health status information to a dedicated register. The host device may perform a read on the readout register to obtain the health status information, as indicated by the one or more values, and may adjust operating procedures or take other actions based on the received health status information.

公开(公告)号：US20230420065A1

公开(公告)日：2023-12-28

申请号：US17851721

申请日：2022-06-28

Applicant: Micron Technology, Inc.

Inventor： Scott E. Schaefer

IPC: G11C29/04

CPC classification number: G11C29/04

Abstract: Methods, systems, and devices for memory fault notification are described. A memory device may receive a configuration corresponding to a circuit node of the memory device, where the circuit node may be selectively coupled with a set of resistors. The memory device may determine a fault condition and couple the circuit node to at least a first resistor based on determining the fault condition. The memory device may bias the circuit node to a first voltage value that satisfies a voltage threshold based on coupling the circuit node to the first resistor. The memory device may output an indication of a fault state to notify a host device that a fault has been detected.

公开(公告)号：US11789818B2

公开(公告)日：2023-10-17

申请号：US17690772

申请日：2022-03-09

Applicant: Micron Technology, Inc.

Inventor： Scott E. Schaefer ,  Aaron P. Boehm

IPC: G06F11/10 ,  H03M13/29

CPC classification number: G06F11/1076 ,  H03M13/2906

Abstract: Methods, systems, and devices for coordinated error correction are described. A memory device indicates, to an external device, that errors were detected in data that was stored by the memory device and requested by the external device based on a comparison between an error correction code stored when the data was written to a memory array and an error correction code generated when the data is read from the memory array. Based on a result of the comparison, an indication of whether the compared error correction codes match is provided to the external device. The external device uses the indication to detect errors in the received version of the data, to manage data storage in the memory device, or both.

公开(公告)号：US11789647B2

公开(公告)日：2023-10-17

申请号：US17098096

申请日：2020-11-13

Applicant: Micron Technology, Inc.

Inventor： Aaron P. Boehm ,  Scott E. Schaefer

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0671 ,  G06F2212/7209

Abstract: Methods, systems, and devices for address verification for a memory device are described. When a memory device receives a write command, the memory device may store, in association with the data written, an indication of a write address associated with the write command. When the memory device receives a read command, the memory device may retrieve data and a previously stored write address associated with the retrieved data, and the memory device may verify a read address associated with the read command against the previously stored write address associated with retrieved data. Thus, for example, the memory device may verify whether data read from the memory array based on an address associated with a read command is data that, when previously written to the memory array, was written in response to a write command associated with a matching address.

公开(公告)号：US11762585B2

公开(公告)日：2023-09-19

申请号：US17180503

申请日：2021-02-19

Applicant: Micron Technology, Inc.

Inventor： Aaron P. Boehm ,  Scott E. Schaefer

IPC: G06F3/06 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/22

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0653 ,  G06F3/0673 ,  G11C11/221 ,  G11C11/4087 ,  G11C11/4091

Abstract: Methods, systems, and devices related to operating a memory array are described. A system may include a memory device and a host device. A memory device may indicate information about a temperature of the memory device, which may include sending an indication to the host device after receiving a signal that initializes the operation of the memory device or storing an indication, for example in a register, about the temperature of the memory device. The information may include an indication that a temperature of the memory device or a rate of change of the temperature of the memory device has satisfied a threshold. Operation of the memory device, or the host device, or both may be modified based on the information about the temperature of the memory device. Operational modifications may include delaying a sending or processing of memory commands until the threshold is satisfied.

公开(公告)号：US20230161491A1

公开(公告)日：2023-05-25

申请号：US18100825

申请日：2023-01-24

Applicant: Micron Technology, Inc.

Inventor： Scott E. Schaefer ,  Aaron P. Boehm

IPC: G06F3/06

CPC classification number: G06F3/0632 ,  G06F3/0679 ,  G06F3/0655 ,  G06F3/0604

Abstract: Methods, systems, and devices for refresh counters in a memory system are described. In some examples, a memory device may include two or more counters configured to increment a respective count based on refresh operations performed on a memory array. A comparison may be made between two or more of the respective counts, which may include determining a difference between the respective counts or a difference in rate of incrementing. A memory device may transmit an indication to a host device based on determining a difference between counters, and the memory device, the host device, or both, may perform various operations or enter various operational modes based on the determined difference.