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公开(公告)号：US12026042B2
公开(公告)日：2024-07-02
申请号：US17858731
申请日：2022-07-06
Applicant: Micron Technology, Inc.
Inventor： Charles See Yeung Kwong , Seungjune Jeon , Wei Wang , Zhenming Zhou
CPC classification number: G06F11/076 , G06F11/008 , G06F11/073 , G06F2201/81 , G06F2212/7211
Abstract: A set of blocks of a memory device comprising a plurality of dies is identified. A block within the set of blocks is identified. The identified block is associated with a capability metric that reflects a projected reliability of the die on which the block resides. Responsive to determining that the capability metric satisfies a condition, a cycle threshold associated with the die is identified. Responsive to determining that a cycle count value derived from a program/erase cycle counter associated with the die matches the cycle threshold, the set of blocks is updated by excluding the block from the set of blocks. A program operation is performed with respect to the updated set of blocks.
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32.发明公开公开(公告)号：US20240062839A1
公开(公告)日：2024-02-22
申请号：US17892437
申请日：2022-08-22
Applicant: Micron Technology, Inc.
Inventor： Wei Wang , Seungjune Jeon , Yang Liu , Charles See Yeung Kwong
CPC classification number: G11C16/3431 , G11C16/0483
Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations comprising performing a data integrity check on a set of memory cells of a source management unit of the memory device to obtain a data integrity metric value; determining whether the data integrity metric value satisfies a first threshold; responsive to determining that the data integrity metric value fails to satisfy the first threshold, determining whether the data integrity metric value satisfies a second threshold that is lower than the first threshold; responsive to determining that the data integrity metric value satisfies the second threshold, causing the memory device to copy data from the source management unit to a destination set of pages of the memory device; and performing a subsequent data integrity check on one or more invalid pages of the source management unit.
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公开(公告)号：US11901014B2
公开(公告)日：2024-02-13
申请号：US17739741
申请日：2022-05-09
Applicant: Micron Technology, Inc.
Inventor： Zhongguang Xu , Nicola Ciocchini , Zhenlei Shen , Charles See Yeung Kwong , Murong Lang , Ugo Russo , Niccolo' Righetti
CPC classification number: G11C16/102 , G11C16/08 , G11C16/26 , G11C16/3481
Abstract: A processing device in a memory sub-system initiates a partial block handling protocol for a closed block of a memory device, the block comprising a plurality of wordlines. The processing device further sends a first programming command to the memory device to program one or more wordlines of the block with first padding data having a first data pattern, wherein the one or more wordlines are adjacent to a last wordline of the block programmed before the block was closed. In addition, the processing device sends a second programming command to the memory device to program all of a set of remaining wordlines of the block with second padding data having a second data pattern comprising fewer bits of data per cell than the first data pattern.
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Patent Agency Ranking
公开(公告)号：US20230360704A1
公开(公告)日：2023-11-09
申请号：US17739741
申请日：2022-05-09
Applicant: Micron Technology, Inc.
Inventor： Zhongguang Xu , Nicola Ciocchini , Zhenlei Shen , Charles See Yeung Kwong , Murong Lang , Ugo Russo , Niccolo' Righetti
CPC classification number: G11C16/102 , G11C16/08 , G11C16/26 , G11C16/3481
Abstract: A processing device in a memory sub-system initiates a partial block handling protocol for a closed block of a memory device, the block comprising a plurality of wordlines. The processing device further sends a first programming command to the memory device to program one or more wordlines of the block with first padding data having a first data pattern, wherein the one or more wordlines are adjacent to a last wordline of the block programmed before the block was closed. In addition, the processing device sends a second programming command to the memory device to program all of a set of remaining wordlines of the block with second padding data having a second data pattern comprising fewer bits of data per cell than the first data pattern.
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公开(公告)号：US11790998B2
公开(公告)日：2023-10-17
申请号：US17411278
申请日：2021-08-25
Applicant: Micron Technology, Inc.
Inventor： Tingjun Xie , Zhenming Zhou , Zhenlei Shen , Charles See Yeung Kwong
CPC classification number: G11C16/3418 , G11C16/08 , G11C16/102 , G11C16/24 , G11C16/26
Abstract: A plurality of memory units residing in a first location of a memory device is identified, wherein the first location of the memory device corresponds to a first layer of a plurality of layers of the memory device. It is determined whether a write disturb capability associated with the first location of the memory device satisfies a threshold criterion. Responsive to determining that the write disturb capability associated with the first location of the memory device satisfies the threshold criterion, a plurality of logical addresses associated with the plurality of memory units is remapped to a second location of the memory device, wherein the second location of the memory device corresponds to a second layer of the plurality of layers of the memory device, and wherein a write disturb capability associated with the second location of the memory device does not satisfy the threshold criterion.
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36.发明授权公开(公告)号：US11756604B2
公开(公告)日：2023-09-12
申请号：US17946612
申请日：2022-09-16
Applicant: Micron Technology, Inc.
Inventor： Charles See Yeung Kwong , Seungjune Jeon
IPC: G11C11/406 , G11C29/42 , G11C11/4096
CPC classification number: G11C11/40622 , G11C11/4096 , G11C11/40615 , G11C29/42
Abstract: A memory access operation performed on a first memory unit of a memory device is detected. A counter associated with the first memory unit is modified. It is determined that the counter satisfies a threshold criterion, wherein the threshold criterion is based on a random or pseudo-random number within a margin of an average number of memory access operations. A refresh operation is performed on a second memory unit.
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公开(公告)号：US20210042200A1
公开(公告)日：2021-02-11
申请号：US16534772
申请日：2019-08-07
Applicant: Micron Technology, Inc.
Inventor： Tingjun Xie , Charles See Yeung Kwong
Abstract: A system includes a memory device with multiple memory dies and at least a spare memory die. A processing device is coupled to the memory device. The processing device is to track a value of a write counter representing a number of write operations performed at the multiple memory dies. The processing device is to activate the spare memory die in response to detection of a failure of a first memory die of the multiple memory dies. The processing device is to store an offset value of the write counter in response to the detection of the activation of the spare memory die, the offset value representing the value of the write counter upon activation of the first spare memory die.
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公开(公告)号：US20210020229A1
公开(公告)日：2021-01-21
申请号：US16514840
申请日：2019-07-17
Applicant: Micron Technology, Inc.
Inventor： Tingjun Xie , Seungjune Jeon , Zhengang Chen , Zhenlei Shen , Charles See Yeung Kwong
IPC: G11C11/406 , G11C11/16
Abstract: A refresh operation can be performed at a memory sub-system The refresh operation can performed at a current frequency. A write count associated with the memory sub-system can be received. A determination can be made as to whether the write count associated with the memory sub-system satisfies a write count threshold. In response to determining that the write count associated with the memory sub-system satisfies the write count threshold, the refresh operation can be performed at an increased frequency relative to the current frequency.
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