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    3D SEMICONDUCTOR DEVICE AND STRUCTURE WITH BONDING
    31.
    发明申请
    3D SEMICONDUCTOR DEVICE AND STRUCTURE WITH BONDING 有权

    公开(公告)号：US20220130684A1

    公开(公告)日：2022-04-28

    申请号：US17567680

    申请日：2022-01-03

    Applicant: Monolithic 3D Inc.

    Inventor： Zvi Or-Bach ,  Brian Cronquist ,  Deepak Sekar

    IPC: H01L21/48 ,  H01L23/498 ,  H01L23/34 ,  H01L27/02 ,  H01L21/8234 ,  H01L27/06 ,  H01L27/098 ,  H01L23/522 ,  H01L23/367 ,  H01L27/092 ,  H01L25/00 ,  H01L23/60 ,  H01L25/065

    Abstract: A 3D semiconductor device, the device including: a first level, where the first level includes a first layer, the first layer including first transistors, and where the first level includes a second layer, the second layer including first interconnections; a second level overlaying the first level, where the second level includes a third layer, the third layer including second transistors, and where the second level includes a fourth layer, the fourth layer including second interconnections; and a plurality of connection paths, where the plurality of connection paths provides connections from a plurality of the first transistors to a plurality of the second transistors, where the second level is bonded to the first level, where the bonded includes oxide to oxide bond regions, where the bonded includes metal to metal bond regions, and where the device includes a plurality of capacitors.

    3D semiconductor device and structure
    33.
    发明授权
    3D semiconductor device and structure 有权

    公开(公告)号：US10600657B2

    公开(公告)日：2020-03-24

    申请号：US16113860

    申请日：2018-08-27

    Applicant: Monolithic 3D Inc.

    Inventor： Zvi Or-Bach ,  Brian Cronquist ,  Deepak Sekar

    IPC: H01L21/48 ,  H01L23/498 ,  H01L21/8234 ,  H01L23/34 ,  H01L27/098 ,  H01L27/092 ,  H01L27/02 ,  H01L27/06 ,  H01L25/065 ,  H01L23/60 ,  H01L23/522 ,  H01L25/00 ,  H01L23/373 ,  H01L23/367

    Abstract: A 3D semiconductor device, the device including: a first single crystal layer including a plurality of first transistors and a first metal layer, where the first metal layer includes interconnecting the first transistors forming, at least in part a plurality of logic gates; a plurality of second transistors overlaying, at least in part the first single crystal layer; a plurality of third transistors overlaying, at least in part the second transistors; a second metal layer overlaying, at least in part the third transistors; Input/Output pads to provide connection to external devices, a local power grid to distribute power to the plurality of logic gates, where the third transistors are aligned to the first transistors with less than 40 nm misalignment, where the first single crystal layer includes an Serializer/Deserializer (“SerDes”) structure connected to at least one of the Input/Output pads, where a memory cell includes at least one of the third transistors.

    3D SEMICONDUCTOR DEVICE AND STRUCTURE
    34.
    发明申请
    3D SEMICONDUCTOR DEVICE AND STRUCTURE 审中-公开

    公开(公告)号：US20190019693A1

    公开(公告)日：2019-01-17

    申请号：US16115519

    申请日：2018-08-28

    Applicant: Monolithic 3D Inc.

    Inventor： Zvi Or-Bach ,  Brian Cronquist ,  Deepak Sekar

    IPC: H01L21/48 ,  H01L23/34 ,  H01L23/498 ,  H01L27/098 ,  H01L27/092 ,  H01L27/02 ,  H01L21/8234 ,  H01L27/06 ,  H01L25/065 ,  H01L23/60 ,  H01L23/522

    Abstract: A 3D semiconductor device, the device including: a first single crystal layer including a plurality of first transistors and a first metal layer, where the first metal layer includes interconnecting the first transistors forming, at least in part a plurality of logic gates; a plurality of second transistors overlaying, at least in part the first single crystal layer; a plurality of third transistors overlaying, at least in part the second transistors; a second metal layer overlaying, at least in part the third transistors; Input/Output pads to provide connection to external devices, a local power grid to distribute power to the logic gates, where the third transistors are aligned to the first transistors with less than 40 nm misalignment, where the first single crystal layer includes a Phase Lock Loop (“PLL”) structure connected to at least one of the Input/Output pads, where a memory cell includes at least one of the third transistors.

    3D SEMICONDUCTOR DEVICE AND STRUCTURE
    35.
    发明申请
    3D SEMICONDUCTOR DEVICE AND STRUCTURE 审中-公开

    公开(公告)号：US20190006192A1

    公开(公告)日：2019-01-03

    申请号：US16114211

    申请日：2018-08-28

    Applicant: Monolithic 3D Inc.

    Inventor： Zvi Or-Bach ,  Brian Cronquist ,  Deepak Sekar

    IPC: H01L21/48 ,  H01L23/34 ,  H01L23/498 ,  H01L27/098 ,  H01L27/02 ,  H01L21/8234 ,  H01L27/06 ,  H01L25/065 ,  H01L27/092 ,  H01L23/60 ,  H01L23/522

    Abstract: A 3D semiconductor device, the device including: a first single crystal layer including a plurality of first transistors and a first metal layer, where the first metal layer includes interconnecting the first transistors forming, at least in part a plurality of logic gates; a plurality of second transistors overlaying, at least in part the first single crystal layer; a plurality of third transistors overlaying, at least in part the second transistors; a plurality of fourth transistors overlaying, at least in part the third transistors; a second metal layer overlaying, at least in part the fourth transistors; where the fourth transistors are aligned with less than 100 nm misalignment to the first transistors, where at least one of the plurality of vias has a radius of less than 200 nm, where a memory cell includes at least one of the third transistors.

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