公开(公告)号：US07672166B2

公开(公告)日：2010-03-02

申请号：US11955891

申请日：2007-12-13

申请人： Ki-Tae Park ,  Yeong-Taek Lee ,  Ki-Nam Kim ,  Doo-Gon Kim

发明人： Ki-Tae Park ,  Yeong-Taek Lee ,  Ki-Nam Kim ,  Doo-Gon Kim

IPC分类号： G11C16/06

CPC分类号： G11C16/3418 ,  G11C16/24 ,  G11C16/3427

摘要： Provided are methods for programming in a non-volatile memory device, using incremental step pulses as a program voltage that is applied to a selected wordline. Methods may include applying a precharge voltage to an even bitline and an odd bitline such that the even bitline and the odd bitline are alternately charged with the precharge voltage and a boosted voltage that is higher than the precharge voltage. Methods may further include applying a bitline voltage corresponding to program data to a selected bitline of the even bitline and the odd bitline.

摘要翻译： 提供了用于在非易失性存储器件中进行编程的方法，其使用增量步长脉冲作为施加到选定字线的编程电压。 方法可以包括将预充电电压施加到偶数位线和奇数位线，使得偶数位线和奇数位线以预充电电压和高于预充电电压的升压电压交替地充电。 方法还可以包括将对应于程序数据的位线电压应用于偶位线和奇数位线的选定位线。

公开(公告)号：US07611948B2

公开(公告)日：2009-11-03

申请号：US11945477

申请日：2007-11-27

申请人： Jae-Hwang Sim ,  Yong-Sik Yim ,  Ki-Nam Kim ,  Jae-Kwan Park

发明人： Jae-Hwang Sim ,  Yong-Sik Yim ,  Ki-Nam Kim ,  Jae-Kwan Park

IPC分类号： H01L21/8247 ,  H01L21/8222

CPC分类号： H01L27/11524 ,  H01L27/115 ,  H01L27/11521 ,  Y10S438/954

摘要： A method of forming a non-volatile memory device includes forming first mask patterns, which can have relatively large distances therebetween. A distance regulating layer is formed that conformally covers the first mask patterns. Second mask patterns are formed in grooves on the distance regulating layer between the first mask patterns.

摘要翻译： 形成非易失性存储器件的方法包括形成第一掩模图案，它们之间的距离可以相对较大。 形成保形地覆盖第一掩模图案的距离调节层。 在第一掩模图案之间的距离调节层的凹槽中形成第二掩模图案。

公开(公告)号：US20090206387A1

公开(公告)日：2009-08-20

申请号：US12070422

申请日：2008-02-19

申请人： Chang-Seok Kang ,  Ki-Nam Kim

发明人： Chang-Seok Kang ,  Ki-Nam Kim

IPC分类号： H01L29/792 ,  H01L21/336 ,  H01L21/28

CPC分类号： H01L27/11568 ,  H01L21/28282 ,  H01L29/4234 ,  H01L29/792

摘要： A non-volatile memory device has improved operating characteristics. The non-volatile memory device includes an active region; a wordline formed on the active region to cross the active region; and a charge trapping layer interposed between the active region and the wordline, wherein a cross region of the active region and the wordline includes an overlap region in which the charge trapping layer is disposed and a non-overlap region in which the charge trapping layer is not disposed.

摘要翻译： 非易失性存储器件具有改进的操作特性。 非易失性存储器件包括有源区; 在有源区域上形成的跨越有源区域的字线; 以及插入在有源区域和字线之间的电荷俘获层，其中有源区域和字线的交叉区域包括其中设置电荷捕获层的重叠区域和电荷捕获层是非重叠区域 没有处理

公开(公告)号：US07560760B2

公开(公告)日：2009-07-14

申请号：US11859958

申请日：2007-09-24

申请人： Hyun-Ho Kim ,  Dong-Jin Jung ,  Ki-Nam Kim ,  Sang-Don Nam ,  Kyu-Mann Lee

发明人： Hyun-Ho Kim ,  Dong-Jin Jung ,  Ki-Nam Kim ,  Sang-Don Nam ,  Kyu-Mann Lee

IPC分类号： H01L27/115

CPC分类号： H01L27/11502 ,  G11C11/22 ,  H01L27/11507

摘要： A ferroelectric memory device includes a microelectronic substrate and a plurality of ferroelectric capacitors on the substrate, arranged as a plurality of row and columns in respective row and column directions. A plurality of parallel plate lines overlie the ferroelectric capacitors and extend along the row direction, wherein a plate line contacts ferroelectric capacitors in at least two adjacent rows. The plurality of plate lines may include a plurality of local plate lines, and the ferroelectric memory device may further include an insulating layer disposed on the local plate lines and a plurality of main plate lines disposed on the insulating layer and contacting the local plate lines through openings in the insulating layer. In some embodiments, ferroelectric capacitors in adjacent rows share a common upper electrode, and respective ones of the local plate lines are disposed on respective ones of the common upper electrodes. Ferroelectric capacitors in adjacent rows may share a common ferroelectric dielectric region. Related fabrication methods are discussed.

摘要翻译： 铁电存储器件包括微电子衬底和在衬底上的多个铁电电容器，被布置为在行和列方向上的多个行和列。 多个平行板线覆盖在铁电电容器上并沿着行方向延伸，其中板线在至少两个相邻行中接触铁电电容器。 多个板线可以包括多个局部板线，并且铁电存储器件还可以包括设置在局部板线上的绝缘层和设置在绝缘层上的多个主板线，并且使本地板线通过 绝缘层中的开口。 在一些实施例中，相邻行中的铁电电容器共享公共上电极，并且各自的局部板线设置在相应的公共上电极上。 相邻行中的铁电电容器可以共享公共铁电电介质区域。 讨论相关的制造方法。

公开(公告)号：US20080111171A1

公开(公告)日：2008-05-15

申请号：US11811931

申请日：2007-06-12

申请人： Heung-Jin Joo ,  Yoon-Jong Song ,  Ki-Nam Kim

发明人： Heung-Jin Joo ,  Yoon-Jong Song ,  Ki-Nam Kim

IPC分类号： H01L29/94 ,  H01L21/02

CPC分类号： H01L27/11502 ,  H01L27/11507 ,  H01L28/55

摘要： In a node structure under a capacitor in a ferroelectric random access memory device and a method of forming the same, top surfaces of the node structures are disposed at substantially the same level as a top surface of an interlayer insulating layer surrounding the node structures, and thus crystal growth of a ferroelectric in the capacitor can be stabilized. To this end, a node insulating pattern is formed on a semiconductor substrate. A node defining pattern surrounding the node insulating pattern is disposed under the node insulating pattern. A node conductive pattern is disposed between the node defining pattern and the node insulating pattern.

摘要翻译： 在铁电随机存取存储器件中的电容器下的节点结构及其形成方法中，节点结构的顶表面设置在与节点结构周围的层间绝缘层的顶表面基本相同的水平处，并且 因此可以使电容器中的铁电体的晶体生长稳定。 为此，在半导体衬底上形成节点绝缘图案。 定义节点绝缘图案周围的节点的节点设置在节点绝缘图案之下。 节点导电图案设置在节点限定图案和节点绝缘图案之间。

公开(公告)号：US20080025065A1

公开(公告)日：2008-01-31

申请号：US11859958

申请日：2007-09-24

申请人： Hyun-Ho Kim ,  Dong-Jin Jung ,  Ki-Nam Kim ,  Sang-Don Nam ,  Kyu-Mann Lee

发明人： Hyun-Ho Kim ,  Dong-Jin Jung ,  Ki-Nam Kim ,  Sang-Don Nam ,  Kyu-Mann Lee

IPC分类号： G11C11/22

CPC分类号： H01L27/11502 ,  G11C11/22 ,  H01L27/11507

摘要： A ferroelectric memory device includes a microelectronic substrate and a plurality of ferroelectric capacitors on the substrate, arranged as a plurality of row and columns in respective row and column directions. A plurality of parallel plate lines overlie the ferroelectric capacitors and extend along the row direction, wherein a plate line contacts ferroelectric capacitors in at least two adjacent rows. The plurality of plate lines may include a plurality of local plate lines, and the ferroelectric memory device may further include an insulating layer disposed on the local plate lines and a plurality of main plate lines disposed on the insulating layer and contacting the local plate lines through openings in the insulating layer. In some embodiments, ferroelectric capacitors in adjacent rows share a common upper electrode, and respective ones of the local plate lines are disposed on respective ones of the common upper electrodes. Ferroelectric capacitors in adjacent rows may share a common ferroelectric dielectric region. Related fabrication methods are discussed.

摘要翻译： 铁电存储器件包括微电子衬底和在衬底上的多个铁电电容器，被布置为在行和列方向上的多个行和列。 多个平行板线覆盖在铁电电容器上并沿着行方向延伸，其中板线在至少两个相邻行中接触铁电电容器。 多个板线可以包括多个局部板线，并且铁电存储器件还可以包括设置在局部板线上的绝缘层和设置在绝缘层上的多个主板线，并且使本地板线通过 绝缘层中的开口。 在一些实施例中，相邻行中的铁电电容器共享公共上电极，并且各自的局部板线设置在相应的公共上电极上。 相邻行中的铁电电容器可以共享公共铁电电介质区域。 讨论相关的制造方法。

公开(公告)号：US20070268749A1

公开(公告)日：2007-11-22

申请号：US11802282

申请日：2007-05-22

申请人： Dae-Mann Kim ,  Wook-Hyun Kwon ,  Ki-Nam Kim ,  Chan-Kwang Park ,  Sang-Pil Sim

发明人： Dae-Mann Kim ,  Wook-Hyun Kwon ,  Ki-Nam Kim ,  Chan-Kwang Park ,  Sang-Pil Sim

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： G11C16/10 ,  G11C11/5671 ,  G11C16/0483 ,  G11C16/3409 ,  G11C16/345

摘要： A method of operating a non-volatile memory device is disclosed. The memory cell includes a channel region separating a source region and a drain region, a tunnel insulating layer, a charge storage layer, and a gate electrode formed over the channel region. The method includes applying a negative voltage to the gate electrode and applying a positive voltage to at least one of the source and drain regions to inject holes into the tunnel insulating layer and thereby remove electrons trapped in the tunnel insulating layer.

摘要翻译： 公开了一种操作非易失性存储器件的方法。 存储单元包括分离源极区和漏极区的沟道区，隧道绝缘层，电荷存储层和形成在沟道区上的栅电极。 该方法包括向栅电极施加负电压并向源区和漏区中的至少一个施加正电压，以将空穴注入到隧道绝缘层中，从而去除俘获在隧道绝缘层中的电子。

公开(公告)号：US20060124988A1

公开(公告)日：2006-06-15

申请号：US11291142

申请日：2005-11-30

申请人： Sung-Hoi Hur ,  Jung-Dal Choi ,  Kyeong-Tae Kim ,  Jong-Ho Park ,  Jae-Duk Lee ,  Ki-Nam Kim

发明人： Sung-Hoi Hur ,  Jung-Dal Choi ,  Kyeong-Tae Kim ,  Jong-Ho Park ,  Jae-Duk Lee ,  Ki-Nam Kim

IPC分类号： H01L21/82 ,  H01L21/8238

CPC分类号： H01L27/115 ,  H01L27/11521

摘要： A semiconductor memory device is fabricated by forming an active region protruding from a semiconductor substrate, forming an isolation layer on the substrate adjacent opposing sidewalls of the active region, and forming a floating gate electrode on a surface of the active region between the opposing sidewalls thereof. The floating gate electrode is formed to extend beyond edges of the surface of the active region onto the isolation layer. A surface of the floating gate electrode adjacent the active region defines a plane, and the isolation layer is confined between the plane and the substrate. A control gate electrode is formed on a surface of the floating gate electrode opposite the active region. The control gate electrode may be formed to extend along sidewalls of the floating gate electrode towards the substrate beyond the plane defined by the surface of the floating gate electrode adjacent the active region. Related devices are also discussed.

摘要翻译： 半导体存储器件通过形成从半导体衬底突出的有源区域形成，在邻近有源区域的相对侧壁的衬底上形成隔离层，以及在其相对侧壁之间的有源区域的表面上形成浮栅电极 。 浮栅电极被形成为延伸超过有源区表面的边缘到隔离层上。 邻近有源区的浮栅电极的表面限定了一个平面，隔离层被限制在平面和衬底之间。 控制栅电极形成在浮动栅电极的与有源区相对的表面上。 控制栅电极可以被形成为沿着浮置栅电极的侧壁朝着衬底延伸超过由邻近有源区的浮栅的表面限定的平面。 还讨论了相关设备。

公开(公告)号：US06909134B2

公开(公告)日：2005-06-21

申请号：US10721689

申请日：2003-11-24

申请人： Yoon-Jong Song ,  Ki-Nam Kim ,  Sang-Woo Lee

发明人： Yoon-Jong Song ,  Ki-Nam Kim ,  Sang-Woo Lee

IPC分类号： H01L27/105 ,  H01L21/8246 ,  H01L27/115 ,  H01L27/108

CPC分类号： H01L27/11502 ,  H01L27/11507

摘要： A ferroelectric memory device and a method for manufacturing the same. The ferroelectric memory device comprises a lower interlayer insulating layer formed on a semiconductor substrate. The ferroelectric memory device further comprises at least two adjacent ferroelectric capacitors disposed on the lower interlayer insulating layer, an interlayer insulation layer formed over the ferroelectric capacitors, leaving a top surface of the ferroelectric capacitors exposed, a patterned via etch-stop layer formed on the interlayer insulation layer, leaving the top surface of the capacitors exposed, an upper interlayer insulating layer formed on the patterned via etch-stop layer, and a plate line commonly connected to the at least two adjacent ferroelectric capacitors. Thus, integration of the ferroelectric memory device can be substantially increased.

摘要翻译： 铁电存储器件及其制造方法。 铁电存储器件包括形成在半导体衬底上的下层间绝缘层。 铁电存储器件还包括设置在下层间绝缘层上的至少两个相邻的铁电电容器，形成在强电介质电容器上的层间绝缘层，留下暴露的铁电电容器的顶表面，形成在其上的图案化通孔蚀刻停止层 层间绝缘层，使电容器的顶表面暴露，形成在图案化通孔蚀刻停止层上的上层间绝缘层，以及通常连接到至少两个相邻铁电电容器的板线。 因此，可以显着增加铁电存储器件的集成。

公开(公告)号：US20050006680A1

公开(公告)日：2005-01-13

申请号：US10775016

申请日：2004-02-10

申请人： Yoon-Jong Song ,  Nak-Won Jang ,  Ki-Nam Kim

发明人： Yoon-Jong Song ,  Nak-Won Jang ,  Ki-Nam Kim

IPC分类号： H01L27/105 ,  H01L21/8246 ,  H01L27/115 ,  H01L29/76

CPC分类号： H01L27/11502 ,  H01L27/11507 ,  H01L28/55 ,  H01L28/65

摘要： Pursuant to embodiments of the present invention, ferroelectric memory devices are provided which comprise a transistor that is provided on an active region in a semiconductor substrate, and a capacitor that has a bottom electrode, a capacitor-ferroelectric layer and a top electrode. These devices may further include at least one planarizing layer that is adjacent to the side surfaces of the bottom electrode such that the top surface of the planarizing layer(s) and the top surface of the bottom electrode form a planar surface. The capacitor-ferroelectric may be formed on this planar surface. The device may also include a plug that electrically connects the bottom electrode to a source-drain region of the transistor. The ferroelectric memory devices according to embodiments of the present invention may reduce ferroelectric degradation of the capacitor.

摘要翻译： 根据本发明的实施例，提供了包括设置在半导体衬底中的有源区上的晶体管和具有底电极，电容器 - 铁电层和顶电极的电容器的铁电存储器件。 这些装置还可以包括与底部电极的侧表面相邻的至少一个平坦化层，使得平坦化层的顶表面和底部电极的顶表面形成平坦的表面。 电容器 - 铁电体可以形成在该平坦表面上。 器件还可以包括将底部电极电连接到晶体管的源极 - 漏极区域的插头。 根据本发明实施例的铁电存储器件可以减小电容器的铁电性能降低。