公开(公告)号：US20230170191A1

公开(公告)日：2023-06-01

申请号：US17931916

申请日：2022-09-14

Applicant: NGK Insulators, Ltd.

Inventor： Seiya INOUE ,  Tatsuya KUNO ,  Ikuhisa MORIOKA

IPC: H01J37/32 ,  H01L21/683

CPC classification number: H01J37/32724 ,  H01L21/6833 ,  H01J2237/002 ,  H01J2237/2007

Abstract: A wafer placement table has a wafer placement surface that allows a wafer to be placed thereon. The wafer placement table includes a ceramic substrate having a built-in electrode, a cooling substrate including a refrigerant flow path, a metal joining layer that joins the ceramic substrate to the cooling substrate, and a plurality of small protrusions disposed on a reference plane of the wafer placement surface. The top surfaces of the small protrusions can support the lower surface of a wafer. The top surfaces of all the small protrusions are located on the same plane. In a flow path overlapping range of the wafer placement surface in which the wafer placement surface overlaps the refrigerant flow path in plan view, an area ratio of the small protrusions is minimized in a portion facing a most upstream portion of the refrigerant flow path.

公开(公告)号：US20210394320A1

公开(公告)日：2021-12-23

申请号：US17462048

申请日：2021-08-31

Applicant: NGK INSULATORS, LTD.

Inventor： Hiroshi TAKEBAYASHI ,  Kenichiro AIKAWA ,  Tatsuya KUNO

IPC: B23Q3/15 ,  H01L21/683 ,  B23K1/00 ,  B23K1/19 ,  H01L21/687

Abstract: An electrostatic chuck includes a ceramic base, a ceramic dielectric layer, an electrostatic electrode, and a ceramic insulating layer. The ceramic dielectric layer is positioned on the ceramic base and is thinner than the ceramic base. The electrostatic electrode is embedded between the ceramic dielectric layer and the ceramic base. The ceramic insulating layer is positioned on the ceramic dielectric layer and is thinner than the ceramic dielectric layer. The ceramic insulating layer has a higher volume resistivity and withstand voltage than the ceramic dielectric layer, and the ceramic dielectric layer has a higher dielectric constant than the ceramic insulating layer.

公开(公告)号：US20250149368A1

公开(公告)日：2025-05-08

申请号：US18651927

申请日：2024-05-01

Applicant: NGK INSULATORS, LTD.

Inventor： Taro USAMI ,  Tatsuya KUNO

IPC: H01L21/683

Abstract: A member for semiconductor manufacturing apparatus includes: a ceramic plate having a wafer placement surface on its upper surface and a built-in electrode; a base plate provided on a lower surface of the ceramic plate; a base plate through-hole that penetrates the base plate in an up-down direction; an insulating tube inserted into the base plate through-hole; an adhesive agent pool provided in at least one of an inner circumferential surface of the base plate through-hole or an outer circumferential surface of the insulating tube, and disposed at a position down away from an upper surface of the insulating tube; and an adhesive layer including an insulating tube outer circumferential surface adhesion part formed from the lower surface of the ceramic plate to an intermediate point of the adhesive agent pool.

公开(公告)号：US20240290646A1

公开(公告)日：2024-08-29

申请号：US18461611

申请日：2023-09-06

Applicant: NGK INSULATORS, LTD.

Inventor： Masaki ISHIKAWA ,  Tatsuya KUNO ,  Yusuke OGISO

IPC: H01L21/683 ,  H01J37/32

CPC classification number: H01L21/6833 ,  H01J37/32715 ,  H01J2237/2007

Abstract: A wafer placement table includes: a ceramic plate having a wafer placement surface on an upper surface and a built-in electrode; a plug placement hole extending through the ceramic plate from a lower surface to the upper surface; a plug placed in the plug placement hole and allowing gas to pass therethrough; and a plug joint joining an outer edge of an upper surface of the plug and an upper opening edge of the plug placement hole and covering the outer edge of the upper surface of the plug from above.

公开(公告)号：US20240038567A1

公开(公告)日：2024-02-01

申请号：US18170129

申请日：2023-02-16

Applicant: NGK Insulators, Ltd.

Inventor： Seiya INOUE ,  Tatsuya KUNO ,  Natsuki HIRATA ,  Kenji YONEMOTO

IPC: H01L21/683

CPC classification number: H01L21/6833 ,  H01J37/32724

Abstract: A member for a semiconductor manufacturing apparatus, includes: a ceramic plate that has a ceramic plate through hole; an electroconductive base plate that has a base plate through hole and that is disposed on a lower surface side of the ceramic plate; an insulating sleeve which is inserted into the base plate through hole and of which an outer peripheral surface is adhered to an inner peripheral surface of the base plate through hole via an adhesion layer; and a sleeve through hole that passes through the insulating sleeve in the up-down direction and that communicates with the ceramic plate through hole. The insulating sleeve has a tool engaging portion that is engageable with an external tool, and upon being engaged with the external tool, the tool engaging portion transmits rotation torque of the external tool to the insulating sleeve.

公开(公告)号：US20230343565A1

公开(公告)日：2023-10-26

申请号：US18171837

申请日：2023-02-21

Applicant: NGK Insulators, Ltd.

Inventor： Tatsuya KUNO ,  Seiya INOUE

IPC: H01J37/32 ,  H01L21/683

CPC classification number: H01J37/32724 ,  H01L21/6833 ,  H01J2237/2007 ,  H01J2237/002

Abstract: A wafer placement table includes: a ceramic substrate having a wafer placement surface at an upper surface, and incorporating an electrode; a cooling substrate which is bonded to a lower surface of the ceramic substrate, and in which a refrigerant flow path is formed; a power supply terminal connected to the electrode; and a power supply terminal hole vertically penetrating the cooling substrate and storing the power supply terminal. The power supply terminal hole intersects with the refrigerant flow path.

公开(公告)号：US20230343564A1

公开(公告)日：2023-10-26

申请号：US18170025

申请日：2023-02-16

Applicant: NGK Insulators, Ltd.

Inventor： Seiya INOUE ,  Tatsuya KUNO

IPC: H01J37/32

CPC classification number: H01J37/32724 ,  H01J37/32807

Abstract: A wafer placement table includes a ceramic substrate having a wafer placement surface on an upper surface thereof and containing an electrode therein; a conductive substrate disposed adjacent to a lower surface of the ceramic substrate, serving also as a plasma generating electrode, and having the same diameter as the ceramic substrate; a support substrate disposed adjacent to a lower surface of the conductive substrate, having a greater diameter than the conductive substrate, and electrically insulated from the conductive substrate; and a mounting flange constituting a part of the support substrate and radially extending out of the conductive substrate.

公开(公告)号：US20230238224A1

公开(公告)日：2023-07-27

申请号：US18056802

申请日：2022-11-18

Applicant: NGK Insulators, Ltd.

Inventor： Seiya INOUE ,  Tatsuya KUNO ,  Shinya YOSHIDA ,  Tomoki NAGAE ,  Yusuke OGISO ,  Takuya YOTO

IPC: H01J37/32 ,  H01L21/683

CPC classification number: H01J37/32715 ,  H01J37/3244 ,  H01L21/6833 ,  H01J2237/327

Abstract: A member for semiconductor manufacturing apparatus has a ceramic plate, a porous plug, an insulating lid, and pores. The ceramic plate has a wafer placement surface as an upper surface. The porous plug is disposed in a plug insertion hole penetrating the ceramic plate in an up-down direction, and allows a gas to flow. The insulating lid is provided in contact with an upper surface of the porous plug, and exposed to the wafer placement surface. A plurality of pores are provided in the insulating lid, and penetrate the insulating lid in an up-down direction.

公开(公告)号：US20230146815A1

公开(公告)日：2023-05-11

申请号：US17819663

申请日：2022-08-15

Applicant: NGK Insulators, Ltd.

Inventor： Seiya INOUE ,  Tatsuya KUNO ,  Ikuhisa MORIOKA

IPC: H01L21/687 ,  H01L21/67

CPC classification number: H01L21/68714 ,  H01L21/67109

Abstract: A wafer placement table includes a ceramic base having a wafer placement surface on its top surface where a wafer is able to be placed and incorporating an electrode; a cooling base having a refrigerant flow channel; and a bonding layer that bonds the ceramic base with the cooling base, wherein in an area that overlaps the wafer placement surface in plan view of the refrigerant flow channel, a cross-sectional area of the refrigerant flow channel at a most downstream part of the refrigerant flow channel is less than the cross-sectional area at a most upstream part of the refrigerant flow channel.

公开(公告)号：US20230115033A1

公开(公告)日：2023-04-13

申请号：US17809567

申请日：2022-06-29

Applicant: NGK Insulators, Ltd.

Inventor： Tatsuya KUNO ,  Seiya INOUE

IPC: H01L21/683

Abstract: A member for semiconductor manufacturing apparatus includes a ceramic plate that has an upper surface including a wafer placement surface and that contains an electrode; a plug insertion hole that is formed as at least a portion of a through-hole extending through the ceramic plate in an up-down direction, an internal thread portion being on an inner circumferential surface around the plug insertion hole; and an insulating plug that includes an external thread portion screwed on the internal thread portion on an outer circumferential surface and that allows gas to pass therethrough.