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公开(公告)号：US11204832B2
公开(公告)日：2021-12-21
申请号：US16838118
申请日：2020-04-02
Applicant: NXP B.V.
Inventor： Jan-Peter Schat
Abstract: A method is provided for detecting a cold boot attack in a data processing system. The data processing system includes a processor, a memory with ECC, and a monitor circuit. In the method, during a boot process of the data processing system, the monitor circuit counts read and write accesses to the memory and maintains a count of the number of errors in the memory detected by the ECC. The read and write access count and the error count are used to detect suspicious activity that may indicate a cold boot attack on the memory. A data processing system that implements the method is also provided.
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公开(公告)号：US20210351922A1
公开(公告)日：2021-11-11
申请号：US17301780
申请日：2021-04-14
Applicant: NXP B.V.
Inventor： Jan-Peter Schat , Fabrice Poulard , Andreas Lentz
Abstract: A method for securing an integrated circuit chip includes obtaining a first value from a first storage area in the chip, obtaining a second value from a second storage area in the chip, generating a third value based on the first value and the second value, and converting a first opcode command obfuscated as a second opcode command into a non-obfuscated form of the first opcode command based on the third value. The first value corresponds to a physically unclonable function (PUF) of the chip. The second value is a key including information indicating a type of obfuscation performed to obfuscate the first opcode command as the second opcode command. The third value may be an inversion flag indicating a type of obfuscation performed to obfuscate the first opcode command as the second opcode command.
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公开(公告)号：US11169952B2
公开(公告)日：2021-11-09
申请号：US16848223
申请日：2020-04-14
Applicant: NXP B.V.
Inventor： Jan-Peter Schat , Ling Wang , Michael Zimin
IPC: G06F13/42
Abstract: The disclosure relates to a data transmission interface for use in a first integrated circuit (IC) for encoding and sending a data packet from the first IC to a second IC via a data bus having four data wires, the data transmission interface arranged to generate four time-dependent binary signals which jointly encode the data packet in signal edges thereof, each of the signals being associated with a unique wire of the data bus and spanning a temporal cycle T within which are defined four consecutive time stamps T1 . . . T4 at which edges can occur in the signals, the data transmission interface further arranged to transmit the signals to the second IC substantially in parallel on their respective data wires, wherein: irrespective of the data packet content, at each time stamp T1 . . . T4 at least one of the four signals has an edge to enable clock recovery at the second IC.
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34.发明授权公开(公告)号：US11146252B2
公开(公告)日：2021-10-12
申请号：US16799053
申请日：2020-02-24
Applicant: NXP B.V.
Inventor： Jan-Peter Schat
Abstract: One specific example involves an integrated circuit that has application logic circuitry which includes flip-flop circuits susceptible to degradations of setup and hold times relative to specified minimum setup and hold times for signals to be processed by the respective flip-flop circuits. In a method carried out by the integrated circuit, timing-based logic states of the flip-flop circuits are controlled, based on at least one transition-scan pattern processed by the flip-flop circuits as part of the application logic circuitry; and respective logic states are set for those flip-flops, which due to degradations of the actual setup and hold times do not satisfy anymore the originally specified minimum setup and hold times.
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公开(公告)号：US20210239753A1
公开(公告)日：2021-08-05
申请号：US17115236
申请日：2020-12-08
Applicant: NXP B.V.
Inventor： Abdellatif Zanati , Henrik Asendorf , Jan-Peter Schat , Nicolas Lamielle
IPC: G01R31/311 , H01Q1/22 , H01P3/12
Abstract: A test apparatus and method for testing a semiconductor device. The semiconductor device includes an integrated circuit and a plurality of external radiating elements located at a surface of the device. The external radiating elements include at least one transmit element and receive element. The test apparatus includes a plunger. The plunger includes a dielectric portion having a surface for placing against the surface of the device. The plunger also includes at least one waveguide. Each waveguide extends through the plunger for routing electromagnetic radiation transmitted by one of the transmit elements of the device to one of the receive elements of the device. Each waveguide comprises a plurality of waveguide openings for coupling electromagnetically to corresponding radiating elements of the device. The dielectric portion is configured to provide a matched interface for the electromagnetic coupling of the waveguide openings to the plurality of external radiating elements of the device.
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Patent Agency Ranking
公开(公告)号：US20200372152A1
公开(公告)日：2020-11-26
申请号：US16417821
申请日：2019-05-21
Applicant: NXP B.V.
Inventor： Jan-Peter Schat
Abstract: An apparatus includes integrated circuitry (IC) and a further circuit. The IC includes internal circuits having sensitive/secret data (SSD) to be maintained as confidential relative to a suspect Hardware Trojan (HT) and including access ports through which information associated with the internal circuits is accessible by external circuitry associated with the HT. The further circuit to learn behavior of the internal circuits that is unique to the integrated circuitry under different operating conditions involving the internal circuits, involving the SSD and involving other data that is functionally associated with an application of the integrated circuitry.
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公开(公告)号：US20200213119A1
公开(公告)日：2020-07-02
申请号：US16237633
申请日：2018-12-31
Applicant: NXP B.V.
Inventor： Jan-Peter Schat
Abstract: This specification discloses devices and methods for a security concept that includes an immobile hardware token (e.g., a “wall token” that is fixed within a wall) which ensures that the more sensitive actions of electronic banking (e.g., money transfers of large sums to foreign bank accounts) can only be done from the account owner's home, but not from a remote place. However, other less sensitive (and lower security risk) actions can still be done from anywhere else. In some embodiments, the hardware token includes sensors to ensure that the token is not moved or tampered with, interfaces to provide distance bounding, and a crypto-processor to provide secure authentication. The distance bounding can be used to determine if the authentication device is in close proximity to the hardware token, which can in turn ensure that the authentication device is within the account owner's home.
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公开(公告)号：US20200073786A1
公开(公告)日：2020-03-05
申请号：US16411052
申请日：2019-05-13
Applicant: NXP B.V
Inventor： Jan-Peter Schat , Xavier Hours , Andres Barrilado Gonzalez
IPC: G06F11/36 , G06F11/26 , G01R31/3181 , G01R31/3167
Abstract: An integrated circuit device is disclosed. The device includes a circuit configured to perform a function, a fault management component, at least one user register, an analog test bus component, a built-in self-test component, a safety monitor component, and gating logic. Additionally, the circuit is separated from the fault management component, the at least one user register, the analog test bus component, the built-in self-test component, the safety monitor, and the gating logic.
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公开(公告)号：US10573107B2
公开(公告)日：2020-02-25
申请号：US16042252
申请日：2018-07-23
Applicant: NXP B.V.
Inventor： Jan-Peter Schat
IPC: G07C9/00 , G01S13/93 , B60R25/24 , G01S13/931
Abstract: A method is provided for authenticating a transceiver in a keyless entry system for a vehicle. The method uses a collision avoidance radar system on the vehicle for authenticating a key fob radar transceiver. A lower power radar signal is transmitted from the vehicle. The lower power radar signal is transmitted below an ambient noise level to make the radar signal difficult for an attacker to detect. The key fob transceiver is then authenticated as being a legitimate transceiver for accessing the vehicle using the low power radar signal. A distance bounding scheme may be used to determine if the key fob is within a predetermined distance. Challenge/response communications may be used to authenticate that the key fob is the legitimate key fob.
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公开(公告)号：US10396974B1
公开(公告)日：2019-08-27
申请号：US16041027
申请日：2018-07-20
Applicant: NXP B.V.
Inventor： Jan-Peter Schat , Ulrich Moehlmann
Abstract: An apparatus includes signal control circuitry, a phase-locked loop (PLL), and a correlation circuit. The signal control circuitry provides a reference clock signal carrying pseudo-random phase noise and as derived from an application clock signal and pseudo-random noise. The PLL, responsive to the reference clock signal carrying the pseudo-random phase noise, provides an output signal that is related to the phase of the reference clock signal. The correlation circuit self-tests the PLL by cross-correlating a signal corresponding to the output signal from the phase detector with the pseudo-random noise and, in response, by assessing results of the cross-correlation relative to a known threshold indicative of a performance level of the PLL.
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