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100 条记录 (耗时 0.049 秒)

    Chip design and fabrication method optimized for profit
    32.
    发明授权
    Chip design and fabrication method optimized for profit 有权
    芯片设计和制造方法优化利润

    公开(公告)号：US08086988B2

    公开(公告)日：2011-12-27

    申请号：US12467326

    申请日：2009-05-18

    申请人： Nathan Buck ,  Howard H. Chen ,  James P. Eckhardt ,  Eric A. Foreman ,  James C. Gregerson ,  Peter A. Habitz ,  Susan K. Lichtensteiger ,  Chandramouli Visweswariah ,  Tad J. Wilder

    发明人： Nathan Buck ,  Howard H. Chen ,  James P. Eckhardt ,  Eric A. Foreman ,  James C. Gregerson ,  Peter A. Habitz ,  Susan K. Lichtensteiger ,  Chandramouli Visweswariah ,  Tad J. Wilder

    IPC分类号： G06F9/455 ,  G06F17/50

    CPC分类号： G06F17/5045 ,  G06F17/5031

    摘要： Disclosed is a computer-implemented method for designing a chip to optimize yielding parts in different bins as a function of multiple diverse metrics and further to maximize the profit potential of the resulting chip bins. The method separately calculates joint probability distributions (JPD), each JPD being a function of a different metric (e.g., performance, power consumption, etc.). Based on the JPDs, corresponding yield curves are generated. A profit function then reduces the values of all of these metrics (e.g., performance values, power consumption values, etc.) to a common profit denominator (e.g., to monetary values indicating profit that may be associated with a given metric value). The profit function and, more particularly, the monetary values can be used to combine the various yield curves into a combined profit-based yield curve from which a profit model can be generated. Based on this profit model, changes to the chip design can be made in order to optimize yield as a function of all of the diverse metrics (e.g., performance, power consumption, etc.) and further to maximize the profit potential of the resulting chips.

    摘要翻译： 公开了一种计算机实现的方法，用于设计芯片以优化不同仓中的产量部分作为多个不同度量的函数，并进一步最大化所得到的芯片仓的利润潜力。 该方法分别计算联合概率分布（JPD），每个JPD是不同度量（例如，性能，功耗等）的函数。 基于JPD，生成相应的收益率曲线。 利润函数然后将所有这些度量（例如，绩效值，功耗值等）的值减小到公共利润分母（例如，指示可能与给定度量值相关联的利润的货币值）。 更具体地说，利润函数，尤其是货币价值可用于将各种收益率曲线组合成基于利润的收益率曲线，从中可以生成利润模型。 基于这种利润模型，可以对芯片设计进行改变，以便根据所有不同的指标（例如性能，功耗等）来优化产量，并进一步最大化所得芯片的利润潜力 。

    Prioritizing of nets for coupled noise analysis
    37.
    发明授权
    Prioritizing of nets for coupled noise analysis 失效
    耦合噪声分析网优先级

    公开(公告)号：US07181711B2

    公开(公告)日：2007-02-20

    申请号：US10908101

    申请日：2005-04-27

    申请人： Eric A. Foreman ,  Peter A. Habitz ,  Gregory M. Schaeffer

    发明人： Eric A. Foreman ,  Peter A. Habitz ,  Gregory M. Schaeffer

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5031

    摘要： A system and method of performing microelectronic chip timing analysis, wherein the method comprises identifying failing timing paths in a chip; prioritizing the failing timing paths in the chip according to a size of random noise events occurring in each timing path; attributing a slack credit statistic for all but highest order random noise events occurring in each timing path; and calculating a worst case timing path scenario based on the prioritized failing timing paths and the slack credit statistic. Preferably, the random noise events comprise non-clock events. Moreover, the random noise events may comprise victim/aggressor net groups belonging to different regularity groups. Preferably, the size of random noise events comprises coupled noise delta delays due to the random noise events occurring in the chip.

    摘要翻译： 一种执行微电子芯片定时分析的系统和方法，其中所述方法包括识别芯片中的故障定时路径; 根据每个定时路径中发生的随机噪声事件的大小对芯片中的故障定时路径进行优先级排序; 归因于每个定时路径中发生的所有但最高阶随机噪声事件的松弛信用统计; 以及基于优先顺序的故障定时路径和松弛信用统计量来计算最坏情况的定时路径情景。 优选地，随机噪声事件包括非时钟事件。 此外，随机噪声事件可以包括属于不同规则组的受害者/侵略者网络组。 优选地，由于芯片中发生的随机噪声事件，随机噪声事件的大小包括耦合的噪声增量延迟。

    Method to quickly estimate inductance for timing models
    38.
    发明授权
    Method to quickly estimate inductance for timing models 有权
    快速估计定时模型电感的方法

    公开(公告)号：US07750648B2

    公开(公告)日：2010-07-06

    申请号：US12059275

    申请日：2008-03-31

    申请人： Eric A. Foreman ,  Peter A. Habitz ,  Mark R. Lasher ,  William J. Livingstone ,  Gregory M. Schaeffer

    发明人： Eric A. Foreman ,  Peter A. Habitz ,  Mark R. Lasher ,  William J. Livingstone ,  Gregory M. Schaeffer

    IPC分类号： G01R27/00

    CPC分类号： G01R27/2611 ,  G01R27/28 ,  G06F17/5036 ,  G06F2217/84

    摘要： A method of estimating an inductance delay includes determining a resistance-capacitance (RC) delay with resistances and capacitances of a network and estimating an inductance delay of the network by determining a propagation delay of an electromagnetic (EM) field across wires of the network. Additionally, the method includes determining if the RC delay is below a specified threshold and adding the estimated inductance delay to the RC delay to determine a total time to propagate voltage swings through the network if the RC delay is below the specified threshold.

    摘要翻译： 估计电感延迟的方法包括通过确定网络的电线（EM）场的传播延迟来确定网络的电阻和电容的电阻 - 电容（RC）延迟并估计网络的电感延迟。 此外，该方法包括确定RC延迟是否低于指定的阈值，并将估计的电感延迟与RC延迟相加，以确定如果RC延迟低于指定阈值，则传播通过网络的电压摆幅的总时间。

    METHOD TO QUICKLY ESTIMATE INDUCTANCE FOR TIMING MODELS
    39.
    发明申请
    METHOD TO QUICKLY ESTIMATE INDUCTANCE FOR TIMING MODELS 有权
    快速估计时序模型电感的方法

    公开(公告)号：US20090243630A1

    公开(公告)日：2009-10-01

    申请号：US12059275

    申请日：2008-03-31

    申请人： Eric A. Foreman ,  Peter A. Habitz ,  Mark R. Lasher ,  William J. Livingstone ,  Gregory M. Schaeffer

    发明人： Eric A. Foreman ,  Peter A. Habitz ,  Mark R. Lasher ,  William J. Livingstone ,  Gregory M. Schaeffer

    IPC分类号： G01R27/28

    CPC分类号： G01R27/2611 ,  G01R27/28 ,  G06F17/5036 ,  G06F2217/84

    摘要： A method of estimating an inductance delay includes determining a resistance-capacitance (RC) delay with resistances and capacitances of a network and estimating an inductance delay of the network by determining a propagation delay of an electromagnetic (EM) field across wires of the network. Additionally, the method includes determining if the RC delay is below a specified threshold and adding the estimated inductance delay to the RC delay to determine a total time to propagate voltage swings through the network if the RC delay is below the specified threshold.

    摘要翻译： 估计电感延迟的方法包括通过确定网络的电线（EM）场的传播延迟来确定网络的电阻和电容的电阻 - 电容（RC）延迟并估计网络的电感延迟。 此外，该方法包括确定RC延迟是否低于指定的阈值，并将估计的电感延迟与RC延迟相加，以确定如果RC延迟低于指定阈值，则传播通过网络的电压摆幅的总时间。

    Device history based delay variation adjustment during static timing analysis
    40.
    发明授权
    Device history based delay variation adjustment during static timing analysis 有权
    静态时序分析期间基于设备历史的延迟变化调整

    公开(公告)号：US08108816B2

    公开(公告)日：2012-01-31

    申请号：US12484293

    申请日：2009-06-15

    申请人： Eric A. Foreman ,  Peter A. Habitz ,  David J. Hathaway ,  Jeffrey G. Hemmett ,  Kerim Kalafala ,  Jeffrey P. Soreff

    发明人： Eric A. Foreman ,  Peter A. Habitz ,  David J. Hathaway ,  Jeffrey G. Hemmett ,  Kerim Kalafala ,  Jeffrey P. Soreff

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5031 ,  G06F17/504 ,  G06F2217/84

    摘要： A system and method for the adjustment of history based delay variation during static timing analysis of an integrated circuit design. The method may include obtaining information through sources of variability of history based components of delay variability, and a relationship between the sources of variability and one or more bounded device histories. Then, inputting history bounds for at least one signal of the integrated circuit design, and computing and propagating history bounds through at least one first segment of the integrated circuit design to at least one signal of the integrated circuit design. Further, the method may include evaluating from at least one of the propagated history bounds, device history bounds for at least one second segment of the integrated circuit design, and based on the evaluated device history bounds, adjusting at least one of a value of the history based delay variability and propagation of timing.

    摘要翻译： 一种用于在集成电路设计的静态时序分析期间调整基于历史的延迟变化的系统和方法。 该方法可以包括通过延迟变异性的基于历史的组件的变异源获得信息，以及变异源与一个或多个有界设备历史之间的关系。 然后，为集成电路设计的至少一个信号输入历史界限，并且通过集成电路设计的至少一个第一段将集成电路设计的至少一个信号计算和传播历史界限。 此外，该方法可以包括从至少一个传播的历史界限评估集成电路设计的至少一个第二段的设备历史界限，以及基于所评估的设备历史界限，调整至少一个 基于历史的延迟变异性和时间传播。