公开(公告)号：US20220376068A1

公开(公告)日：2022-11-24

申请号：US17326095

申请日：2021-05-20

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Hui Zang ,  Gang Chen

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L27/146

Abstract: Transistors include a pyramid-shaped gate trench defined by a triangular shape or a trapezoidal shape in a channel width plane and a trapezoidal shape in a channel length plane. Side wall portions of the pyramid-shaped gate trench form a channel having a triangular shape or a trapezoidal shape in the channel width plane. Advantageously, such transistors increase transconductance without increasing pixel width. Devices, image sensors, and pixels incorporating such transistors are also provided, in addition to methods of manufacturing the same.

公开(公告)号：US20220375977A1

公开(公告)日：2022-11-24

申请号：US17326103

申请日：2021-05-20

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Hui Zang ,  Gang Chen

IPC: H01L27/146

Abstract: Transistors having nonplanar electron channels in the channel width plane have one or more features that cause the different parts of the nonplanar electron channel to turn on at substantially the same threshold voltage. Advantageously, such transistors have substantially uniform threshold voltage across the nonplanar electron channel. Devices, image sensors, and pixels incorporating such transistors are also provided, in addition to methods of manufacturing the same.

公开(公告)号：US11282886B2

公开(公告)日：2022-03-22

申请号：US16711239

申请日：2019-12-11

Applicant: OmniVision Technologies, Inc.

Inventor： Hui Zang ,  Gang Chen

IPC: H01L27/146

Abstract: A pixel includes a semiconductor substrate, an upper surface thereof forming a trench having a trench depth relative to a planar region of the upper surface surrounding the trench, and in a plane perpendicular to the planar region; an upper width between the planar region and an upper depth that is less than the trench depth; and a lower width, between the upper depth and the trench depth, that is less than the upper width. A floating diffusion region adjacent to the trench extends away from the planar region to a junction depth exceeding the upper depth and is less than the trench depth. The photodiode region in the substrate includes a lower photodiode section beneath the trench and an upper photodiode section adjacent to the trench, beginning at a photodiode depth that is less than the trench depth, extending toward and adjoining the lower photodiode section.

公开(公告)号：US20220020790A1

公开(公告)日：2022-01-20

申请号：US16931229

申请日：2020-07-16

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Hui Zang ,  Cunyu Yang ,  Gang Chen

IPC: H01L27/146 ,  H04N5/33

Abstract: A pixel cell includes a photodiode disposed in a pixel cell region and proximate to a front side of a semiconductor layer to generate image charge in response to incident light directed through a backside to the photodiode. A cell deep trench isolation (CDTI) structure is disposed in the pixel cell region along an optical path of the incident light to the photodiode and proximate to the backside. The CDTI structure includes a central portion extending a first depth from the backside towards the front side. Planar outer portions extend laterally outward from the central portion. The planar output portions further extend a second depth from the backside towards the front side. The first depth is greater than the second depth. Planes formed by each of the planar outer portions intersect in a line coincident with a longitudinal center line of the central portion of the CDTI structure.

公开(公告)号：US20240304638A1

公开(公告)日：2024-09-12

申请号：US18180037

申请日：2023-03-07

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Hui Zang ,  Vincent Venezia

IPC: H01L27/146

CPC classification number: H01L27/14614 ,  H01L27/14643 ,  H01L27/14689 ,  H01L27/14698

Abstract: A pixel cell includes a photodiode disposed in a semiconductor material. A floating diffusion is disposed in the semiconductor material. A transfer gate includes a vertical transfer gate structure disposed in the semiconductor material between the photodiode and the floating diffusion. The transfer gate is coupled between the photodiode and the floating diffusion. A passivation layer is disposed in the semiconductor material and proximate to the vertical transfer gate. The passivation layer has a region with a non-uniformly distributed doping profile proximate to the vertical gate structure such that a first doping concentration of the region in the passivation layer proximate to the vertical gate structure along a first direction is less than a second doping concentration of the region in the passivation layer proximate to the vertical gate structure along a second direction.

公开(公告)号：US11990496B2

公开(公告)日：2024-05-21

申请号：US17568909

申请日：2022-01-05

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Qin Wang ,  Hui Zang

IPC: H01L27/146

CPC classification number: H01L27/14638 ,  H01L27/1463

Abstract: Pixels, such as for image sensors and electronic devices, include a photodiode formed in a semiconductor substrate, a floating diffusion, and a transfer structure selectively coupling the photodiode to the floating diffusion. The transfer structure includes a transfer gate formed on the semiconductor substrate, and a vertical channel structure including spaced apart first doped regions formed in the semiconductor substrate between the transfer gate and the photodiode. Each spaced apart first doped region is doped at a first dopant concentration with a first-type dopant. The spaced apart first doped regions are formed in a second doped region doped at a second dopant concentration with a second-type dopant of a different conductive type.

公开(公告)号：US11978753B2

公开(公告)日：2024-05-07

申请号：US17307789

申请日：2021-05-04

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Yuanliang Liu ,  Hui Zang

IPC: H01L27/146

CPC classification number: H01L27/1463 ,  H01L27/14612 ,  H01L27/14632 ,  H01L27/14687

Abstract: Process to release Silicon stress in forming CMOS image sensor. In one embodiment, a method for manufacturing an image sensor includes providing a first wafer that is a semiconductor substrate, where the first wafer has a first side and a second side opposite from the first side. The method also includes attaching a second wafer to the second side of the first wafer. The method further includes forming isolation structures in the second wafer by etching. The isolation structures are bounded by the second side of the first wafer. The method also includes growing an epitaxial layer between individual isolation structures.

公开(公告)号：US11417701B2

公开(公告)日：2022-08-16

申请号：US16995609

申请日：2020-08-17

Applicant: OmniVision Technologies, Inc.

Inventor： Hui Zang ,  Gang Chen

IPC: H01L27/146 ,  H04N5/353 ,  H04N5/374 ,  H04N5/378

Abstract: A CMOS image sensor has an array of photodiode cells, the photodiode cells each include four buried photodiodes coupled by vertical transfer gate transistors to a single floating node diffusion. Each cell also has a reset transistor coupled to the floating node diffusion, a source follower transistor having gate coupled to the floating node diffusion, and a read select transistor coupled to the source follower transistor. The reset transistor, source follower transistor, and read select transistor have predominately gate and shape edges oriented at an angle greater than 30-degrees and less than 60-degrees from a line extending along an entire horizontal row of photodiodes of a photodiode array of the image sensor and are formed vertically above, and in the same integrated circuit as, the photodiodes of the photodiode array.

公开(公告)号：US11335718B2

公开(公告)日：2022-05-17

申请号：US16931229

申请日：2020-07-16

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Hui Zang ,  Cunyu Yang ,  Gang Chen

IPC: H01L27/146 ,  H04N5/33

Abstract: A pixel cell includes a photodiode disposed in a pixel cell region and proximate to a front side of a semiconductor layer to generate image charge in response to incident light directed through a backside to the photodiode. A cell deep trench isolation (CDTI) structure is disposed in the pixel cell region along an optical path of the incident light to the photodiode and proximate to the backside. The CDTI structure includes a central portion extending a first depth from the backside towards the front side. Planar outer portions extend laterally outward from the central portion. The planar output portions further extend a second depth from the backside towards the front side. The first depth is greater than the second depth. Planes formed by each of the planar outer portions intersect in a line coincident with a longitudinal center line of the central portion of the CDTI structure.

公开(公告)号：US20220005849A1

公开(公告)日：2022-01-06

申请号：US16918929

申请日：2020-07-01

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Hui Zang ,  Gang Chen ,  Kenny Geng

IPC: H01L27/146 ,  H04N5/378

Abstract: An image sensor includes photodiodes disposed in a pixel region and proximate to a front side of a semiconductor layer. A backside metal grating is formed in a backside oxide layer disposed proximate to a backside of the semiconductor layer. A deep trench isolation (DTI) structure with a plurality of pixel region portions and an edge region portion is formed in the semiconductor layer. The pixel region portions are disposed in the pixel region of the semiconductor layer such that incident light is directed through the backside metal grating, through the backside of the semiconductor layer, and between the pixel region portions of the DTI structure to the photodiodes. The edge region portion of the DTI structure is disposed in an edge region outside of the pixel region. The edge region portion of the DTI structure is biased with a DTI bias voltage.