Pointed-trench pixel-array substrate and associated fabrication method

    公开(公告)号:US11810940B2

    公开(公告)日:2023-11-07

    申请号:US17080797

    申请日:2020-10-26

    Inventor: Hui Zang Gang Chen

    CPC classification number: H01L27/14643 H01L27/14603 H01L31/102

    Abstract: A pointed-trench pixel-array substrate includes a floating diffusion region and a photodiode region formed in a semiconductor substrate. The semiconductor substrate includes, between a top surface and a back surface thereof, a sidewall surface and a bottom surface defining a trench extending into the semiconductor substrate away from a planar region of the top surface surrounding the trench. In a cross-sectional plane perpendicular to the top surface and intersecting the floating diffusion region, the photodiode region, and the trench, (i) the bottom surface is V-shaped and (ii) the trench is located between the floating diffusion region and the photodiode region.

    Pyramid-shaped transistors
    4.
    发明授权

    公开(公告)号:US11621336B2

    公开(公告)日:2023-04-04

    申请号:US17326095

    申请日:2021-05-20

    Inventor: Hui Zang Gang Chen

    Abstract: Transistors include a pyramid-shaped gate trench defined by a triangular shape or a trapezoidal shape in a channel width plane and a trapezoidal shape in a channel length plane. Side wall portions of the pyramid-shaped gate trench form a channel having a triangular shape or a trapezoidal shape in the channel width plane. Advantageously, such transistors increase transconductance without increasing pixel width. Devices, image sensors, and pixels incorporating such transistors are also provided, in addition to methods of manufacturing the same.

    Uniform threshold voltage non-planar transistors

    公开(公告)号:US11588033B2

    公开(公告)日:2023-02-21

    申请号:US17326112

    申请日:2021-05-20

    Inventor: Hui Zang Gang Chen

    Abstract: Transistors having nonplanar electron channels in the channel width plane have one or more features that cause the different parts of the nonplanar electron channel to turn on at substantially the same threshold voltage. Advantageously, such transistors have substantially uniform threshold voltage across the nonplanar electron channel. Devices, image sensors, and pixels incorporating such transistors are also provided, in addition to methods of manufacturing the same.

    UNIFORM THRESHOLD VOLTAGE NON-PLANAR TRANSISTORS

    公开(公告)号:US20220376069A1

    公开(公告)日:2022-11-24

    申请号:US17326112

    申请日:2021-05-20

    Inventor: Hui Zang Gang Chen

    Abstract: Transistors having nonplanar electron channels in the channel width plane have one or more features that cause the different parts of the nonplanar electron channel to turn on at substantially the same threshold voltage. Advantageously, such transistors have substantially uniform threshold voltage across the nonplanar electron channel. Devices, image sensors, and pixels incorporating such transistors are also provided, in addition to methods of manufacturing the same.

    Metal deep trench isolation biasing solution

    公开(公告)号:US11476290B2

    公开(公告)日:2022-10-18

    申请号:US16918929

    申请日:2020-07-01

    Abstract: An image sensor includes photodiodes disposed in a pixel region and proximate to a front side of a semiconductor layer. A backside metal grating is formed in a backside oxide layer disposed proximate to a backside of the semiconductor layer. A deep trench isolation (DTI) structure with a plurality of pixel region portions and an edge region portion is formed in the semiconductor layer. The pixel region portions are disposed in the pixel region of the semiconductor layer such that incident light is directed through the backside metal grating, through the backside of the semiconductor layer, and between the pixel region portions of the DTI structure to the photodiodes. The edge region portion of the DTI structure is disposed in an edge region outside of the pixel region. The edge region portion of the DTI structure is biased with a DTI bias voltage.

    Pixel and associated transfer-gate fabrication method

    公开(公告)号:US11462579B2

    公开(公告)日:2022-10-04

    申请号:US16804671

    申请日:2020-02-28

    Inventor: Hui Zang Gang Chen

    Abstract: A method for forming a transfer gate includes (i) forming a dielectric pillar on a surface of a semiconductor substrate and (ii) growing an epitaxial layer on the semiconductor substrate and surrounding the dielectric pillar. The dielectric pillar has a pillar height that exceeds an epitaxial-layer height of the epitaxial layer relative to the surface. The method also includes removing the dielectric pillar to yield a trench in the epitaxial layer. A pixel includes a doped semiconductor substrate having a front surface opposite a back surface. The front surface forms a trench extending a depth zT with respect to the front surface within the doped semiconductor substrate along a direction z perpendicular to the front surface and the back surface. The pixel has a dopant concentration profile, a derivative thereof with respect to direction z being discontinuous at depth zT.

    Pixel array with isolated pixels
    9.
    发明授权

    公开(公告)号:US11329085B2

    公开(公告)日:2022-05-10

    申请号:US16548697

    申请日:2019-08-22

    Inventor: Qin Wang Gang Chen

    Abstract: A pixel array includes a semiconductor substrate, a plurality of isolation layer segments, and a plurality of photodiodes. Each of the plurality of isolation layer segments extends through the semiconductor substrate in a first direction. Each of the plurality of isolation layer segments encloses a portion of the semiconductor substrate in a plane perpendicular to the first direction. The plurality of isolation layer segments form a grid that defines a plurality of isolated sections of the semiconductor substrate. The plurality of isolated sections of the semiconductor substrate include the portions of the semiconductor substrate. Each of the photodiodes is formed in a respective one of the plurality of isolated sections of the semiconductor substrate.

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