Imaging device
    32.
    发明授权

    公开(公告)号:US11653117B2

    公开(公告)日:2023-05-16

    申请号:US17664426

    申请日:2022-05-23

    CPC classification number: H04N25/65 H04N25/77

    Abstract: An imaging device is provided with an amplification transistor having a gate connected to a charge accumulator, a feedback transistor of which the source or drain is electrically connected to the charge accumulator and the other is connected to the source or drain of the amplification transistor, a current supply that supplies a current to a first node, a first select transistor of which the source or drain is connected to the other of the amplification transistor, a second select transistor of which the source or drain is connected to the source or drain of the amplification transistor, a current source/voltage source switching circuit that selectively connects a current source or a first voltage supply circuit to the other of the first select transistor, and a second voltage supply circuit connected to the other of the second select transistor.

    Imaging device
    38.
    发明授权

    公开(公告)号:US10904464B2

    公开(公告)日:2021-01-26

    申请号:US16447148

    申请日:2019-06-20

    Abstract: An imaging device comprising: a first pixel cell including a first photoelectric converter generating a first signal, the first photoelectric converter including a first electrode and a first photoelectric conversion region on the first electrode, and a first circuit coupled to the first electrode and detecting the first signal; and a second pixel cell including a second photoelectric converter generating a second signal, the second photoelectric converter including a second electrode and a second photoelectric conversion region on the second electrode, and a second circuit coupled to the second electrode and detecting the second signal. A sensitivity of the first pixel cell is higher than that of the second pixel cell. A circuit configuration of the first circuit is different from that of the second circuit. The first circuit includes a feedback circuit configured to negatively feed back a voltage of the first electrode to the first electrode.

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