FPGA configuration bitstream protection using multiple keys
    31.
    发明授权
    FPGA configuration bitstream protection using multiple keys 有权
    FPGA配置比特流保护使用多个密钥

    公开(公告)号:US07725738B1

    公开(公告)日:2010-05-25

    申请号:US11042477

    申请日:2005-01-25

    IPC分类号: G06F12/14

    摘要: Circuits, methods, and apparatus that prevent detection and erasure of encoding or encryption keys. These encoding keys may be used to encode a configuration bitstream or other data for an FPGA or other device. An exemplary embodiment of the present invention masks a first key to form an encoding key in order to prevent detection of the first key. In a specific embodiment, the first key is encoded using a second key. The encoded key is used to encode a configuration bitstream or other data. The encoded key is stored on an FPGA or other device. When the device is to be configured, the encoded key is retrieved and used to decode the bitstream or other data. A further embodiment stores an encryption key in a one-time programmable memory (OTP) array to prevent its erasure or modification. The encoding key may be further obfuscated before storage.

    摘要翻译: 阻止检测和擦除编码或加密密钥的电路,方法和装置。 这些编码密钥可以用于对配置比特流或FPGA或其他设备的其他数据进行编码。 本发明的示例性实施例掩蔽第一密钥以形成编码密钥,以便防止第一密钥的检测。 在具体实施例中,使用第二密钥对第一密钥进行编码。 编码密钥用于对配置比特流或其他数据进行编码。 编码密钥存储在FPGA或其他设备上。 当要配置设备时,将检索编码密钥并将其用于解码比特流或其他数据。 另一实施例将加密密钥存储在一次性可编程存储器(OTP)阵列中以防止其擦除或修改。 在存储之前可以进一步模糊编码密钥。

    Voice business client
    32.
    发明申请
    Voice business client 有权
    语音业务客户端

    公开(公告)号:US20080249781A1

    公开(公告)日:2008-10-09

    申请号:US11784105

    申请日:2007-04-04

    IPC分类号: G10L21/00 G06F17/30

    CPC分类号: G10L13/00

    摘要: The subject mater herein relates to computer software and client-server based applications and, more particularly, to a voice business client. Some embodiments include one or more device-agnostic application interaction models and one or more device specific transformation services. Some such embodiments provide one or more of systems, methods, and software embodied at least in part in a device specific transformation service to transform channel agnostic application interaction models to and from device or device surrogate specific formats.

    摘要翻译: 本文的主题涉及计算机软件和基于客户机 - 服务器的应用,更具体地,涉及语音业务客户端。 一些实施例包括一个或多个设备不可知应用交互模型和一个或多个设备特定转换服务。 一些这样的实施例提供至少部分地体现在设备特定转换服务中的系统,方法和软件中的一个或多个,以将信道不可知应用交互模型转换到设备或设备替代特定格式。

    PLD with split multiplexed inputs from global conductors
    35.
    发明授权
    PLD with split multiplexed inputs from global conductors 失效
    PLD具有来自全局导体的分路复用输入

    公开(公告)号:US5942914A

    公开(公告)日:1999-08-24

    申请号:US879309

    申请日:1997-06-19

    IPC分类号: H03K19/173 H03K19/177

    摘要: An improved multiplexer arrangement for connecting global conductors to logic array block (LAB) inputs. A single connection connects a particular global conductor to an input path to LABs on both sides of the interconnect region in a folded LAB architecture. The number of connections to the global conductors is thus reduced, reducing the number of transistors needed to make those connections and the corresponding loading of the global conductors. The connections to two paths are part of a first level multiplexer. A second-level multiplexer connected to each LAB line is also provided to add back some of the flexibility lost by having each global conductor connection connect to two paths. The invention cuts the number of transistors needed to connect to the global conductors in half, while adding some transistors for the second-level multiplexers, with a net reduction in connection transistors of about 1/3.

    摘要翻译: 用于将全局导体连接到逻辑阵列块(LAB)输入的改进的多路复用器布置。 单个连接器将折叠LAB架构中的特定全局导体连接到互连区域两侧的LAB的输入路径。 因此,减少与全局导体的连接数量,减少了进行这些连接所需的晶体管数量以及全局导线的相应负载。 与两条路径的连接是第一级多路复用器的一部分。 还提供连接到每个LAB线路的二级多路复用器,以通过使每个全局导体连接连接到两条路径来补偿一些失去的灵活性。 本发明将连接到全局导体所需的晶体管数量减少一半,同时为第二级多路复用器添加一些晶体管,其中大约+ E,fra 1/3 + EE的连接晶体管的净减少。