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公开(公告)号：US20060146881A1
公开(公告)日：2006-07-06
申请号：US11030344
申请日：2005-01-06
IPC分类号： H04J3/00
CPC分类号： H04L49/901 , H04L49/90 , H04L49/9021
摘要： Apparatus and method for storing network frame data which is to be modified. A plurality of buffers stores the network data which is arranged in a data structure identified by a frame control block and buffer control block. A plurality of buffer control blocks associated with each buffer storing the frame data establishes a sequence of the buffers. Each buffer control block has data for identifying a subsequent buffer within the sequence. The first buffer is identified by a field of a frame control block as well as the beginning and ending address of the frame data. The frame data can be modified without rewriting the data to memory by altering the buffer control block and/or frame control block contents without having to copy or rewrite the data in order to modify it.
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公开(公告)号：US07061860B1
公开(公告)日：2006-06-13
申请号：US09706969
申请日：2000-11-06
IPC分类号： H04J3/14
CPC分类号： H04Q11/0478 , H04L2012/568
摘要： A method for shaping network traffic in a computer network is described for packet data networks. The method includes one or more packet queues for traffic having a plurality of different desired packet transfer rates, each queue being assigned to a connection having a predetermined desired packet transfer rate. Each incoming data packet is directed to the appropriate queue. Each of a plurality of timing circuits operate at a different frequency in a series of frequencies. The frequencies are selected so that the desired packet transfer rate for a connection can be established by summing outputs from more than one of the timing circuits.
摘要翻译： 针对分组数据网络描述了一种用于整形计算机网络中的网络流量的方法。 该方法包括用于具有多个不同期望分组传输速率的业务的一个或多个分组队列，每个队列被分配给具有预定的期望分组传送速率的连接。 每个传入的数据包被引导到适当的队列。 多个定时电路中的每一个在一系列频率中以不同的频率工作。 选择频率使得可以通过对来自多于一个定时电路的输出求和来建立连接的期望分组传送速率。
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公开(公告)号：US20060026342A1
公开(公告)日：2006-02-02
申请号：US10899937
申请日：2004-07-27
IPC分类号： G06F12/00
CPC分类号： G06F13/1642
摘要： Access arbiters are used to prioritize read and write access requests to individual memory banks in DRAM memory devices, particularly fast cycle DRAMs. This serves to optimize the memory bandwidth available for the read and the write operations by avoiding consecutive accesses to the same memory bank and by minimizing dead cycles. The arbiter first divides DRAM accesses into write accesses and read accesses. The access requests are divided into accesses per memory bank with a threshold limit imposed on the number of accesses to each memory bank. The write receive packets are rotated among the banks based on the write queue status. The status of the write queue for each memory bank may also be used for system flow control. The arbiter also typically includes the ability to determine access windows based on the status of the command queues, and to perform arbitration on each access window.
摘要翻译： 访问仲裁器被用于将对DRAM存储器件，特别是快速循环DRAM中的各个存储体的读取和写入访问请求进行优先级排序。 这用于通过避免对同一存储体的连续访问并且通过最小化死循环来优化用于读取和写入操作的存储器带宽。 仲裁器首先将DRAM访问划分为写访问和读访问。 访问请求被划分为每个存储体的访问，并且对每个存储体的访问次数施加了阈值限制。 基于写入队列状态，写入接收数据包在存储体之间旋转。 每个存储体的写入队列的状态也可以用于系统流控制。 仲裁器还通常包括基于命令队列的状态来确定访问窗口的能力，并且在每个访问窗口上执行仲裁。
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公开(公告)号：US20050243850A1
公开(公告)日：2005-11-03
申请号：US11152453
申请日：2005-06-14
申请人： Brian Bass , Jean Calvignac , Anthony Gallo , Marco Heddes , Sridhar Rao , Michael Siegel , Brian Youngman , Fabrice Verplanken
发明人： Brian Bass , Jean Calvignac , Anthony Gallo , Marco Heddes , Sridhar Rao , Michael Siegel , Brian Youngman , Fabrice Verplanken
IPC分类号： G06F15/16 , G06F13/40 , G06F15/177 , H04L12/56
CPC分类号： H04L49/3036 , G06F13/4022 , H04L49/15 , H04L49/205 , H04L49/3009 , H04L49/351
摘要： A network switch apparatus, components for such an apparatus, and methods of operating such an apparatus in which data flow handling and flexibility is enhanced by the cooperation of a control point and a plurality of interface processors formed on a semiconductor substrate. The control point and interface processors together form a network processor capable of cooperating with other elements including an optional switching fabric device in executing instructions directing the flow of data in a network.
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35.发明申请Longest prefix match (LPM) algorithm implementation for a network processor 失效用于网络处理器的最长前缀匹配（LPM）算法实现公开(公告)号：US20050144553A1
公开(公告)日：2005-06-30
申请号：US11045634
申请日：2005-01-28
申请人： Brian Bass , Jean Calvignac , Marco Heddes , Antonios Maragkos , Piyush Patel , Michael Siegel , Fabrice Verplanken
发明人： Brian Bass , Jean Calvignac , Marco Heddes , Antonios Maragkos , Piyush Patel , Michael Siegel , Fabrice Verplanken
CPC分类号： G06F17/30985 , H04L45/7457 , Y10S707/99931 , Y10S707/99933 , Y10S707/99936 , Y10S707/99942 , Y10S707/99943 , Y10S707/99945
摘要： Novel data structures, methods and apparatus for finding the longest prefix match search when searching tables with variable length patterns or prefixes. To find the exact match or the best matching prefix, patterns have to be compared a bit at a time until the exact or first: match is found. This requires “n” number of comparisons or memory accesses to identify the closest matching pattern. The trees are built in such a way that the matching result is guaranteed to be a best match, whether it is an exact match or a longest prefix match. Using the trail of all the birds and associated prefix lengths enables determination of the correct prefix result from the trail. By construction, the search tree provides the best matching prefix at or after the first compare during walking of the trail or tree.
摘要翻译： 当搜索具有可变长度模式或前缀的表时，用于查找最长前缀的新型数据结构，方法和装置匹配搜索。 要找到完全匹配或最佳匹配前缀，模式必须一次比较一下，直到找到完全匹配或第一个匹配。 这需要“n”个比较或存储器访问来识别最接近的匹配模式。 树的建立方式使得匹配结果保证是最佳匹配，无论是完全匹配还是最长匹配前缀。 使用所有鸟的踪迹和相关的前缀长度可以确定路线中正确的前缀结果。 通过构建，搜索树在步道或树的步行期间在第一次比较之前或之后提供最佳的匹配前缀。
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36.发明申请公开(公告)号：US20050076010A1
公开(公告)日：2005-04-07
申请号：US10650327
申请日：2003-08-28
申请人： Brian Bass , Jean Calvignac , Marco Heddes , Antonios Maragkos , Piyush Patel , Michael Siegel , Fabrice Verplanken
发明人： Brian Bass , Jean Calvignac , Marco Heddes , Antonios Maragkos , Piyush Patel , Michael Siegel , Fabrice Verplanken
CPC分类号： H04L45/742 , H04L45/7453 , Y10S707/99933 , Y10S707/99934 , Y10S707/99935 , Y10S707/99936 , Y10S707/99937 , Y10S707/99943 , Y10S707/99945
摘要： Novel data structures, methods and apparatus for finding a full match between a search pattern and a pattern stored in a leaf of the search tree. A key is input, a hash function is performed on the key, a direct table (DT) is accessed, and a tree is walked through pattern search control blocks (PSCBS) until reaching a leaf. The search mechanism uses a set of data structures that can be located in a few registers and regular memory, and then used to build a Patricia tree structure that can be manipulated by a relatively simple hardware macro. Both keys and corresponding information needed for retrieval are stored in the Patricia tree structure. The hash function provides an n->n mapping of the bits of the key to the bits of the hash key. The data structure that is used to store the hash key and the related information in the tree is called a leaf. Each leaf corresponds to a single key that matches exactly with the input key. The leaf contains the key as well as additional information. The length of the leaf is programmable, as is the length of the key. The leaf is stored in random access memory and is implemented as a single memory entry. If the key is located in the direct table then it is called a direct leaf.
摘要翻译： 用于在搜索图案和存储在搜索树的叶中的模式之间找到完全匹配的新型数据结构，方法和装置。 输入密钥，对密钥执行散列函数，访问直接表（DT），并通过模式搜索控制块（PSCBS）走树，直到到达叶。 搜索机制使用一组可以位于几个寄存器和常规内存中的数据结构，然后用于构建可由相对简单的硬件宏操作的Patricia树结构。 检索所需的两个密钥和相应的信息都存储在Patricia树结构中。 散列函数提供密钥的比特到散列密钥的比特的n> n映射。 用于存储散列键和树中相关信息的数据结构称为叶。 每个叶对应于与输入键完全匹配的单个键。 叶包含关键以及其他信息。 叶片的长度是可编程的，密钥的长度也是可编程的。 叶存储在随机存取存储器中，并被实现为单个存储器条目。 如果键位于直接表中，则称为直接叶。
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公开(公告)号：US5444692A
公开(公告)日：1995-08-22
申请号：US161372
申请日：1993-12-02
申请人： Claude Basso , Jean Calvignac , Fabrice Verplanken
发明人： Claude Basso , Jean Calvignac , Fabrice Verplanken
IPC分类号： H04L12/433 , H04L12/56 , H04L12/417
CPC分类号： H04L12/433 , H04L49/3018 , H04L49/3027 , H04L49/351
摘要： The invention includes a bridge having n ports (n>1), each port being connected to a Token-Ring physical segment, each physical segment having one native Token-Ring workstation attached. The bridge to the workstations a single Token-Ring logical segment with a single Active Monitor and a single Ring Number. The invention includes a centralized medium access control (MAC) function inside a centralized processor instead of a MAC function implemented at each port of the bridge; the frame handling function, due to the fixed and limited configuration (same bridge Active Monitor seen by all connected stations), does not require a multi-port bridge function, but a simpler switch function between ports. Bridge clocking is also simplified, and a cost effective unshield twisted pair (UTP) retiming solution is presented.
摘要翻译： 本发明包括具有n个端口（n> 1）的桥，每个端口连接到令牌环物理段，每个物理段具有一个本地令牌环工作站。 工作站的桥接到单个活动监视器和单个环号的单个令牌环逻辑段。 本发明包括集中式处理器内的中央媒体访问控制（MAC）功能，而不是在桥的每个端口处实现的MAC功能; 帧处理功能由于固定和限制配置（所有连接站所见的同一桥主动监视器）不需要多端口桥接功能，而是端口之间更简单的交换机功能。 桥接时钟也被简化，并提出了一种经济有效的非屏蔽双绞线（UTP）重新定时器解决方案。
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公开(公告)号：US20120195208A1
公开(公告)日：2012-08-02
申请号：US13017963
申请日：2011-01-31
CPC分类号： H04L69/22
摘要： A method of operating a packet parser in a computing system includes providing a configurable packet pointer by the packet parser, the packet pointer configured to index a configurable number of atomic parsing elements, the atomic parsing elements having a configurable size, in a data stream received by the computing system for extraction, wherein the indexed atomic parsing elements are non-contiguous in the data stream; and receiving the extracted indexed atomic parsing elements from the data stream by the packet parser.
摘要翻译： 一种在计算系统中操作分组解析器的方法包括：由分组解析器提供可配置的分组指针，所述分组指针被配置为在接收的数据流中索引可配置数量的原子解析元素（所述原子解析元素具有可配置大小） 由所述计算系统提取，其中所述索引的原子解析元素在所述数据流中不连续; 以及由分组解析器从数据流接收提取的索引原子解析元素。
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39.发明申请APPARATUS, METHOD AND PROGRAM PRODUCT TO GENERATE AND USE CRC IN COMMUNICATIONS NETWORK 失效在通信网络中生成和使用CRC的装置，方法和程序产品公开(公告)号：US20080046797A1
公开(公告)日：2008-02-21
申请号：US11875995
申请日：2007-10-22
IPC分类号： H03M13/09
CPC分类号： H04L1/0061 , H04L1/0072 , H04L12/5601 , H04L45/742 , H04L2012/5627 , H04L2012/5656
摘要： The CRC for the CPS Header of an ATM AAL2 cell is generated by a CRC generator which uses the 8 bits of the CID field to generate partial 5 bits CRCs which are loaded in a first table. The 6 bits LI field and 5 bits UUI field are added to the partial 5 bits CRC to form 16 bits. The CRC generator uses the 2.sup.16 bits to generate a second CRC table. The CRC for a particular CPS header is generated by correlating bits in the CID field, LI field and UUI field with the two tables.
摘要翻译： 用于ATM AAL2单元的CPS头的CRC由CRC发生器产生，CRC发生器使用CID字段的8位来产生加载在第一表中的部分5位CRC。 6位LI字段和5位UUI字段被添加到部分5位CRC以形成16位。 CRC生成器使用2.sup.16位来生成第二个CRC表。 通过将CID字段，LI字段和UUI字段中的位与两个表相关来生成特定CPS头的CRC。
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公开(公告)号：US20060245443A1
公开(公告)日：2006-11-02
申请号：US11119329
申请日：2005-04-29
CPC分类号： H04L47/623 , H04L47/50 , H04L47/568
摘要： Systems and methods for scheduling data packets in a network processor are disclosed. Embodiments provide a network processor that comprises a best-effort scheduler with a minimal calendar structure for addressing schedule control blocks. In one embodiment, a four-entry calendar structure provides for rate-limited weighted best effort scheduling. Each of a plurality of different flows has associated schedule control blocks. Schedule control blocks are stored as linked lists in a last-in-first-out buffer. Each calendar entry is associated with a different linked list by storing in the calendar entry the address of the first-out schedule control block in the linked list. Each schedule control block has a counter and is assigned a rate limit according to the bandwidth priority of the flow to which the corresponding packet belongs. Each time a schedule control block is accessed from a last-in-first-out buffer storing the linked list, the scheduler generates a scheduling event and the counter of the schedule control block is incremented. When an incremented counter of a schedule control block equals its rate limit, the schedule control block is temporarily removed from further scheduling until a time interval concludes.
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