公开(公告)号：US20150050785A1

公开(公告)日：2015-02-19

申请号：US14496225

申请日：2014-09-25

Applicant: QUALCOMM Incorporated

Inventor： Bin Yang ,  Xia Li ,  Jun Yuan

IPC: H01L21/8238 ,  H01L21/84 ,  H01L21/28

CPC classification number: H01L21/823814 ,  H01L21/28026 ,  H01L21/823828 ,  H01L21/84 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/42376 ,  H01L29/47 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834

Abstract: A complementary metal-oxide-semiconductor (CMOS) device and methods of formation thereof are disclosed. In a particular example, a method of forming a CMOS device includes forming a first layer on an extension layer of a wafer, forming a first gate on a portion of the first layer, and forming an expansion region proximate to the extension layer. The method also includes removing a portion of the first gate to create a cavity and removing a portion of the first layer to extend the cavity to the extension layer.

Abstract translation: 公开了一种互补金属氧化物半导体（CMOS）器件及其形成方法。 在具体示例中，形成CMOS器件的方法包括在晶片的延伸层上形成第一层，在第一层的一部分上形成第一栅极，以及形成靠近延伸层的扩张区域。 该方法还包括去除第一栅极的一部分以产生空腔并去除第一层的一部分以将空腔延伸到延伸层。

公开(公告)号：US20140264485A1

公开(公告)日：2014-09-18

申请号：US13834594

申请日：2013-03-15

Applicant: QUALCOMM INCORPORATED

Inventor： Xia Li ,  Bin Yang ,  Stanley Seungchul Song

IPC: H01L29/66 ,  G06F17/50 ,  H01L29/78

CPC classification number: H01L27/0924 ,  G06F17/5045 ,  G06F17/5068 ,  H01L21/265 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L29/0607 ,  H01L29/1041 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: An apparatus comprises a substrate and a fin-type semiconductor device extending from the substrate. The fin type semiconductor device comprises a fin that comprises a first region having a first doping concentration and a second region having a second doping concentration. The first doping concentration is greater than the second doping concentration. The fin type semiconductor device also comprises an oxide layer. Prior to source and drain formation of the fin-type semiconductor device, a doping concentration of the oxide layer is less than the first doping concentration.

Abstract translation: 一种装置包括从衬底延伸的衬底和鳍式半导体器件。 翅片型半导体器件包括鳍，其包括具有第一掺杂浓度的第一区域和具有第二掺杂浓度的第二区域。 第一掺杂浓度大于第二掺杂浓度。 翅片型半导体器件还包括氧化物层。 在鳍式半导体器件的源极和漏极形成之前，氧化物层的掺杂浓度小于第一掺杂浓度。

公开(公告)号：US20140252543A1

公开(公告)日：2014-09-11

申请号：US13784895

申请日：2013-03-05

Applicant: QUALCOMM INCORPORATED

Inventor： Xia Li ,  Bin Yang

IPC: H01L49/02

CPC classification number: H01L28/60 ,  H01L23/5223 ,  H01L27/0733 ,  H01L28/88 ,  H01L28/92 ,  H01L29/94 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A particular metal-oxide-metal (MOM) capacitor device includes a conductive gate material coupled to a substrate. The MOM capacitor device further includes a first metal structure coupled to the conductive gate material. The MOM capacitor device further includes a second metal structure coupled to the substrate and proximate to the first metal structure.

Abstract translation: 特定的金属氧化物金属（MOM）电容器器件包括耦合到衬底的导电栅极材料。 MOM电容器装置还包括耦合到导电栅极材料的第一金属结构。 MOM电容器装置还包括耦合到衬底并且靠近第一金属结构的第二金属结构。

公开(公告)号：US12206001B2

公开(公告)日：2025-01-21

申请号：US16526756

申请日：2019-07-30

Applicant: QUALCOMM Incorporated

Inventor： Bin Yang ,  Haining Yang ,  Xia Li

IPC: H01L29/423 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/088

Abstract: A semiconductor device is disclosed that includes a plurality of fins on a substrate. A long channel gate is disposed over a first portion of the plurality of fins. A gate contact is provided having an extended portion that extends into an active area from a gate contact base outside the active area.

公开(公告)号：US11545483B2

公开(公告)日：2023-01-03

申请号：US16712222

申请日：2019-12-12

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Haining Yang ,  Bin Yang

IPC: H01L27/06 ,  H01L29/04 ,  H01L29/06 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/762 ,  H01L29/78

Abstract: Certain aspects of the present disclosure are directed to a semiconductor device. The semiconductor device generally includes a substrate, at least one silicon-on-insulator (SOI) transistor disposed above the substrate, a gate-all-around (GAA) transistor disposed above the substrate, and a fin field-effect transistor (FinFET) disposed above the substrate.

公开(公告)号：US11515406B2

公开(公告)日：2022-11-29

申请号：US16379904

申请日：2019-04-10

Applicant: QUALCOMM Incorporated

Inventor： Gengming Tao ,  Bin Yang ,  Xia Li

IPC: H01L29/737 ,  H01L29/40 ,  H01L29/66 ,  H03F3/19

Abstract: Aspects generally relate to a heterojunction bipolar transistor (HBT), and method of manufacturing the same. The HBT including an emitter a first, a first side of a base coupled to a second side of the emitter opposite the first side of the emitter. A collector coupled to the base on a second side of the base opposite the emitter, wherein an area of a junction between the base and the collector is less than or equal to an area of a junction between the base and the emitter. A dielectric coupled to the collector. A first conductive base contact coupled to the base and adjacent to the collector and extending over a base-collector junction, the conductive base contact operative as a field plate.

公开(公告)号：US10930730B2

公开(公告)日：2021-02-23

申请号：US15816295

申请日：2017-11-17

Applicant: QUALCOMM Incorporated

Inventor： Ye Lu ,  Yun Yue ,  Phanikumar Konkapaka ,  Bin Yang ,  Chuan-Hsing Chen

IPC: H01L23/52 ,  H01L27/08 ,  H01L29/06 ,  H01L23/522 ,  H01L29/78 ,  H01L29/93

Abstract: A metal-oxide-semiconductor (MOS) device for radio frequency (RF) applications may include a guard ring. The guard ring may surround the MOS device and at least one other MOS device. The MOS device may further include a level zero contact layer coupled to a first interconnect layer through level zero interconnects and vias. The first interconnect layer may be for routing to the MOS device.

公开(公告)号：US10923436B2

公开(公告)日：2021-02-16

申请号：US16362951

申请日：2019-03-25

Applicant: QUALCOMM Incorporated

Inventor： Bin Yang ,  Kai Liu ,  Xia Li

IPC: H01L23/00 ,  H01L25/16 ,  H01L23/498 ,  H04W88/02 ,  H04W88/08

Abstract: Certain aspects of the present disclosure provide apparatus for thermal matching of integrated circuits (ICs). One example apparatus generally includes a first substrate, a first IC disposed on the first substrate and having a second substrate, and a second IC disposed on the first substrate. The second IC may include a third substrate, a thermal conductivity adjustment region comprising different material than the third substrate, the thermal conductivity adjustment region being adjacent to a first side of the third substrate, and one or more electrical components formed in one or more layers of the second IC adjacent to a second side of the third substrate, wherein the first side and the second side are opposite sides of the third substrate, and wherein a thermal conductivity of the thermal conductivity adjustment region is closer to a thermal conductivity of the second substrate than a thermal conductivity of the third substrate.

公开(公告)号：US10734384B1

公开(公告)日：2020-08-04

申请号：US16255008

申请日：2019-01-23

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Bin Yang ,  Gengming Tao

IPC: H01L27/092 ,  H01L29/24 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L27/02 ,  H01L21/8238 ,  H01L29/08

Abstract: Vertically-integrated two-dimensional (2D) semiconductor slabs in Complementary Field-Effect Transistor (FET) (CFET) cell circuits are disclosed. A horizontal footprint of a CFET cell circuit may be reduced in an X-axis dimension by reducing a gate length of the N-type and P-type channel structures. The N-type and P-type channel structures may be formed of 2D semiconductor materials with high carrier mobility and strong on/off control, which allows a gate length of each semiconductor channel structure to be reduced without increasing a leakage current. By employing one or more elongated monolayers of 2D material in each slab, and vertically stacking slabs to form each semiconductor channel structure, a desired CFET drive strength may be adjusted according to a vertical dimension of the CFET cell circuit, while X-axis and Y-axis dimensions of the horizontal footprint are reduced.

公开(公告)号：US20200091448A1

公开(公告)日：2020-03-19

申请号：US16130457

申请日：2018-09-13

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Bin Yang ,  Gengming Tao

IPC: H01L51/05 ,  H01L51/00 ,  H01L27/06

Abstract: Three-dimensional (3D) carbon nanotube gate field-effect transistors (FETs), that use carbon nanotubes to form a gate, and related fabrication methods are disclosed. A carbon nanotube gate can provide for greater channel control and enlarge the effective channel width of the 3D FET, thus increasing drive strength. Carbon nanotubes have lower surface scatter and have been found to be diffusive such that resistance dominates carrier transport, thus causing higher carrier mobility. A 3D FET can be provided that includes a gate formed from carbon nanotube(s) disposed adjacent to a semiconductor channel formed from a carbon nanotube(s). A dual-gate FET can be provided employing a carbon nanotube gate(s) comprising a front and back carbon nanotube with a semiconductor channel formed therebetween.