公开(公告)号：US20240371775A1

公开(公告)日：2024-11-07

申请号：US18310388

申请日：2023-05-01

Applicant: QUALCOMM Incorporated

Inventor： Hong Bok WE ,  Joan Rey Villarba BUOT ,  Michelle Yejin KIM ,  Kuiwon KANG

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/00 ,  H01L23/498

Abstract: In an aspect, a substrate includes a core that includes a core dielectric and a first conductive pattern on a first surface of the core dielectric, and a first metallization structure over the first surface of the core dielectric. The first metallization structure includes a first dielectric, and the first dielectric has a first opening formed therein. The substrate further includes a first electronic component disposed in the first opening of the first dielectric, and a first adhesive layer coupling the first electronic component with the core.

公开(公告)号：US20240079307A1

公开(公告)日：2024-03-07

申请号：US17939769

申请日：2022-09-07

Applicant: QUALCOMM Incorporated

Inventor： Wei WANG ,  Kuiwon KANG ,  Michelle Yejin KIM ,  Ahmer SYED

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00

CPC classification number: H01L23/49838 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2924/35121

Abstract: A package comprising an integrated device and a substrate coupled to the integrated device. The substrate comprises at least one dielectric layer and a plurality of interconnects. The plurality of interconnects include a plurality of post interconnects. The plurality of post interconnects include a post interconnect comprising a profile cross section that includes a trapezoid shape.

公开(公告)号：US20210249325A1

公开(公告)日：2021-08-12

申请号：US16789272

申请日：2020-02-12

Applicant: QUALCOMM Incorporated

Inventor： David Fraser RAE ,  John HOLMES ,  Marcus HSU ,  Kuiwon KANG ,  Avantika SODHI

IPC: H01L23/367 ,  H01L23/498 ,  H01L21/56 ,  H01L23/31 ,  H01L23/42

Abstract: A package that includes a first substrate, an integrated device coupled to the first substrate, a second substrate coupled to the integrated device, and an encapsulation layer located between the first substrate and the second substrate. The second substrate is configured to operate as a heat spreader. The second substrate is configured to be free of an electrical connection with the integrated device.

公开(公告)号：US20200381344A1

公开(公告)日：2020-12-03

申请号：US16424700

申请日：2019-05-29

Applicant: QUALCOMM Incorporated

Inventor： Aniket PATIL ,  Hong Bok WE ,  Kuiwon KANG ,  Zhijie WANG

IPC: H01L23/498 ,  H01L23/538 ,  H01L25/16 ,  H01L21/48 ,  H01L23/00

Abstract: Certain aspects of the present disclosure generally relate to a chip package having a split conductive pad for coupling to a device terminal. An example chip package generally includes a layer, a first plurality of conductive pads disposed on the layer, at least one conductive trace disposed on the layer and between the first plurality of conductive pads, and an electrical component having a first terminal coupled to the first plurality of conductive pads and disposed above the at least one conductive trace.

公开(公告)号：US20200350260A1

公开(公告)日：2020-11-05

申请号：US16400264

申请日：2019-05-01

Applicant: QUALCOMM Incorporated

Inventor： Aniket PATIL ,  Kuiwon KANG ,  Zhijie WANG ,  Ming YI

IPC: H01L23/552 ,  H01L23/04 ,  H01L21/52 ,  H01L23/498

Abstract: Certain aspects of the present disclosure provide an integrated circuit (IC) package and techniques for fabricating the IC package. The IC package generally includes a substrate, an IC disposed above the substrate, and a shielding layer coupled to a layer of the substrate, wherein the shielding layer is disposed above the substrate adjacent to the IC, and below an upper surface of the IC.

公开(公告)号：US20200091062A1

公开(公告)日：2020-03-19

申请号：US16131224

申请日：2018-09-14

Applicant: QUALCOMM Incorporated

Inventor： Jaehyun YEON ,  Hong Bok WE ,  Chin-Kwan KIM ,  Kuiwon KANG

IPC: H01L23/498 ,  H01L23/538 ,  H01L23/00 ,  H01L21/68 ,  H05K1/11 ,  H05K1/18 ,  H05K3/46

Abstract: Certain aspects of the present disclosure provide techniques for forming a cavity with various conductive pad interconnections for receiving an electronic component in an integrated circuit. One example method of fabricating an integrated circuit generally includes forming a conductive metal above a first substrate layer, forming a barrier metal above the conductive metal, disposing at least one second substrate layer above the barrier metal, forming a cavity in the at least one second substrate layer by using a laser to expose the barrier metal and the conductive metal in the cavity, and etching the conductive metal in the form of a conductive pad pattern for coupling the conductive metal to an electronic component.

公开(公告)号：US20200051907A1

公开(公告)日：2020-02-13

申请号：US16230896

申请日：2018-12-21

Applicant: QUALCOMM Incorporated

Inventor： Kuiwon KANG ,  Marcus HSU ,  Brigham NAVAJA ,  Houssam JOMAA

IPC: H01L23/522 ,  H01L23/00 ,  H01L23/528 ,  H01L21/768

Abstract: A device that includes a die and a substrate coupled to the die. The substrate includes a dielectric layer and a plurality of embedded interconnects. Each embedded interconnect located through a first planar surface of the substrate such that a first portion of the embedded interconnect is located within the dielectric layer and a second portion of the embedded interconnect is external of the dielectric layer. In some implementations, the substrate includes a core layer. In some implementations, the dielectric layer and the plurality of embedded interconnects may be part of a build up layer of the substrate.

公开(公告)号：US20190393120A1

公开(公告)日：2019-12-26

申请号：US16016888

申请日：2018-06-25

Applicant: QUALCOMM Incorporated

Inventor： Kuiwon KANG ,  Zhijie WANG ,  Bohan YAN

IPC: H01L23/367 ,  H01L23/373 ,  H01L23/498 ,  H01L23/00

Abstract: An integrated circuit package having an interposer with increased thermal conductivity and techniques for fabricating such an integrated circuit package are provided. One example integrated circuit package generally includes a package substrate, at least one semiconductor die disposed above the package substrate, and an interposer disposed above the at least one semiconductor die. The interposer includes a dielectric layer, and a metallic plate disposed adjacent to a first portion of the dielectric layer. The height of the metallic plate is greater than a height of the dielectric layer.

公开(公告)号：US20180269186A1

公开(公告)日：2018-09-20

申请号：US15867518

申请日：2018-01-10

Applicant: QUALCOMM Incorporated

Inventor： Kuiwon KANG ,  Houssam JOMAA ,  Christopher BAHR ,  Layal ROUHANA

IPC: H01L25/10 ,  H01L23/538 ,  H01L21/48 ,  H01L23/498 ,  H01L23/00

Abstract: A package that includes a substrate comprising an interposer interconnect and a cavity, a redistribution portion coupled to the substrate, the redistribution comprising a plurality of redistribution interconnects, and a first die coupled to the redistribution portion through the cavity of the substrate. A substantial region between a side surface of the first die and the substrate is free of an encapsulation layer. In some implementations, the substrate is free of a metal ring that surrounds the first die. In some implementations, the redistribution portion comprises a barrier layer and a first interconnect coupled to the barrier layer. The barrier layer is coupled to the interposer interconnect.