Slave-to-slave direct communication

    公开(公告)号:US10725949B2

    公开(公告)日:2020-07-28

    申请号:US16115388

    申请日:2018-08-28

    Abstract: Methods and apparatuses for operating a direct communication over a serial communication bus are provided. An apparatus includes a master having a host controller. The host controller is configured to communicate with a first slave and with a second slave via a serial communication bus using at least one master-slave address, in accordance with a serial communication protocol. The host controller includes a master-slave module configured to operate communication with the first slave and with the second slave via the serial communication bus in accordance with the serial communication protocol and be in a low-power mode while the first slave and the second slave are in a direct communication. The host controller includes an always-on module configured to, while the master-slave module is in the low-power mode, clock the serial communication bus for the direct communication.

    SECURITY TECHNIQUES FOR A PERIPHERAL COMPONENT INTERCONNECT (PCI) EXPRESS (PCIE) SYSTEM

    公开(公告)号:US20200089645A1

    公开(公告)日:2020-03-19

    申请号:US16569816

    申请日:2019-09-13

    Abstract: Security techniques for a Peripheral Component Interconnect (PCI) express (PCIE) system include a transport layer protocol (TLP) packet that has a prepended TLP prefix indicating the security features of the TLP packet and an integrity check value (ICV) appended to the TLP packet. The ICV is based on the TLP packet and any TLP prefixes including a security prefix. At a receiver, if the ICV does not match, then the receiver has evidence that the TLP packet may have been subjected to tampering. Further, the TLP packet may be encrypted to prevent snooping, and this feature would be indicated in the TLP prefix. Still further, the TLP prefix may include a counter that may be used to prevent replay attacks. PCIE contemplates flexible TLP prefixes, and thus, the standard readily accommodates the addition of a TLP prefix which indicates the security features of the TLP packet.

    Systems and methods for power conservation in a SOUNDWIRE audio bus through pattern recognition

    公开(公告)号:US10528517B1

    公开(公告)日:2020-01-07

    申请号:US16059651

    申请日:2018-08-09

    Abstract: Systems and methods for power conservation in a SOUNDWIRE audio bus provide a pulse density modulated (PDM) audio stream at an audio source to an encoder. The encoder has a plurality of encoding states corresponding to bit patterns. The encoder compares bits of the audio stream to available bit patterns and selects an encoding state. The audio source sends the encoding state to an audio sink and then sends data to the audio sink based on encoding using the selected encoding state. The data is sent over a non-return to zero inverted (NRZI) audio bus. As the audio stream changes bit patterns, the encoder may select different more efficient encoding states and provide updates to the audio sink of changes in the encoding state.

    SPLIT READ TRANSACTIONS OVER AN AUDIO COMMUNICATION BUS

    公开(公告)号:US20190250876A1

    公开(公告)日:2019-08-15

    申请号:US16260299

    申请日:2019-01-29

    CPC classification number: G06F3/162 G06F2213/0002 G06F2213/0026

    Abstract: Systems and methods for providing split read transactions over an audio communication bus are disclosed. In one aspect, a device that receives a read command informs a requester that data is not yet available and to try again at a future time, potentially outside the traditional response window. In the meantime, the receiving device begins fetching the requested data to have available when the requester makes a subsequent request. By providing a not yet response, data may be fetched from a memory element in a low-power state after it has been taken out of the low-power state or data may be fetched from a remote location or over a slow internal bus.

    VIRTUAL GENERAL PURPOSE INPUT/OUTPUT (GPIO) (VGI) OVER A TIME DIVISION MULTIPLEX (TDM) BUS

    公开(公告)号:US20190229824A1

    公开(公告)日:2019-07-25

    申请号:US15878790

    申请日:2018-01-24

    Abstract: Systems and methods for providing virtual general purpose input/output (GPIO) (VGI) over a time division multiplex (TDM) bus are disclosed. While a SOUNDWIRE bus is particularly contemplated, other TDM buses may also be used to provide the benefits outlined herein. In particular, raw GPIO signals are placed into time slots on a TDM bus without requiring additional overhead or packaging. This arrangement allows all drops on a multi-drop bus to receive the GPIO signals substantially concurrently with latency measured in less than a frame period.

    Low latency transmission systems and methods for long distances in soundwire systems

    公开(公告)号:US10356504B2

    公开(公告)日:2019-07-16

    申请号:US15882119

    申请日:2018-01-29

    Abstract: Low latency transmission systems and methods for long distances in SOUNDWIRE systems are disclosed. In an exemplary aspect, a SOUNDWIRE sub-system is coupled to a long cable through a bridge. The bridge converts SOUNDWIRE signals to signals for transmission over the long cable and converts the signals from the long cable to the SOUNDWIRE signals for transmission in the SOUNDWIRE sub-system. Conversion between signal types may include concatenating signals of a similar type into a group that is serially transmitted over the long cable. Concatenation of bit slots in this manner consumes minimal overhead in bus turnaround, thereby reducing latency. In further aspects, the functionality of the bridge may be incorporated into a headset or a mobile terminal.

    IN-BAND RESET AND WAKE UP ON A DIFFERENTIAL AUDIO BUS

    公开(公告)号:US20190121767A1

    公开(公告)日:2019-04-25

    申请号:US16119127

    申请日:2018-08-31

    Abstract: Systems and methods for in-band reset and wake up on a differential audio bus are disclosed. In particular, after entering a low-power mode, a master device opens a drain on a transistor driving the differential audio bus. When a slave device needs the bus to wake, the slave device may transition the state of the bus. On detecting the transition of the bus, the master device may reassert control of the state of the bus and hold the bus in this new state until ready to issue a synchronization sequence. Likewise, an additional aspect of the present disclosure provides a distinctive sequence of holding the bus at a predefined state for an extended duration interrupted by a relatively brief reversal of the state that triggers a reset of all slave devices on the audio bus.

    Full bandwidth communication buses
    40.
    发明授权

    公开(公告)号:US09934178B2

    公开(公告)日:2018-04-03

    申请号:US15059009

    申请日:2016-03-02

    Abstract: Full bandwidth communication buses are disclosed. While primarily focused on the Serial Low-power Inter-chip Media Bus (SLIMbus) communication bus, the concepts of the present disclosure may be extended to other communication buses. Exemplary aspects of the present disclosure utilize a reserved segment distribution code and a segment length to define a Segment Interval that is better-sized relative to raw data bits. By fitting the segment interval to the size of the raw data bits, bandwidth utilization is maximized, resulting in faster effective data transfers. Completion of such efficient data transfers may allow the communication bus to spend more time in a low-power mode and thus, conserve power. Additionally, such efficient data transfers may allow for better quality in presentation of multimedia content to the user.

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