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31.发明授权Multi-processor systems and methods for backup for non-coherent speculative fills 失效用于非相干投机填充的多处理器系统和备份方法公开(公告)号：US07406565B2
公开(公告)日：2008-07-29
申请号：US10756637
申请日：2004-01-13
CPC分类号： G06F9/383 , G06F9/384 , G06F9/3842 , G06F9/3863 , G06F12/0815
摘要： Multi-processor systems and methods are disclosed. One embodiment may comprise a multi-processor system comprising a processor having a processor pipeline that executes program instructions with data from a speculative fill that is provided in response to a source request, and a backup system that retains information associated with a previous processor execution state corresponding to an instruction associated with the speculative fill. The backup system may initiate a backup of the processor pipeline to the previous processor execution state if the speculative fill is determined to be non-coherent, and the processor pipeline may continue execution of program instructions if the speculative fill is determined to be coherent.
摘要翻译： 公开了多处理器系统和方法。 一个实施例可以包括多处理器系统，其包括具有处理器流水线的处理器，处理器流水线通过响应于源请求而提供的来自推测填充的数据执行程序指令，以及备份系统，其保留与先前处理器执行状态相关联的信息 对应于与投机填充相关联的指令。 如果确定推测填充是非相干的，则备用系统可以启动处理器管线的备份到先前的处理器执行状态，并且如果确定推测填充是相干的，则处理器流水线可以继续执行程序指令。
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32.发明授权System and method for conflict responses in a cache coherency protocol with ordering point migration 有权具有排序点迁移的缓存一致性协议中的冲突响应的系统和方法公开(公告)号：US07395374B2
公开(公告)日：2008-07-01
申请号：US10760651
申请日：2004-01-20
IPC分类号： G06F12/00
CPC分类号： G06F12/0831
摘要： Systems and methods are disclosed for interaction between different cache coherency protocols. One system may comprise a home node that receives a request for data from a first node in a first cache coherency protocol. A second node provides a conflict response to a request for the data from the home node. The conflict response indicates that an ordering point for the data is migrating according to a second cache coherency protocol, which is different from the first cache coherency protocol.
摘要翻译： 公开了用于不同高速缓存一致性协议之间的交互的系统和方法。 一个系统可以包括家庭节点，其在第一高速缓存一致性协议中从第一节点接收对数据的请求。 第二节点向来自家节点的数据的请求提供冲突响应。 冲突响应指示数据的排序点根据与第一高速缓存一致性协议不同的第二高速缓存一致性协议进行迁移。
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公开(公告)号：US07376794B2
公开(公告)日：2008-05-20
申请号：US10756636
申请日：2004-01-13
CPC分类号： G06F12/0822
摘要： Multi-processor systems and methods are disclosed. One embodiment may comprise a multi-processor system comprising at least one data fill provided to a source processor in response to a source request by the source processor, and a coherent signal generated by the multi-processor system that provides an indication of which data fill of the at least one data fill is a coherent data fill.
摘要翻译： 公开了多处理器系统和方法。 一个实施例可以包括多处理器系统，其包括响应于源处理器的源请求而提供给源处理器的至少一个数据填充，以及由多处理器系统生成的相干信号，其提供哪个数据填充的指示 所述至少一个数据填充是相干数据填充。
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34.发明授权System and method for responses between different cache coherency protocols 有权用于不同缓存一致性协议之间的响应的系统和方法公开(公告)号：US07177987B2
公开(公告)日：2007-02-13
申请号：US10760436
申请日：2004-01-20
CPC分类号： G06F12/0831 , G06F12/0828 , G06F2212/2542
摘要： Systems and method are disclosed for providing responses for different cache coherency protocols. One embodiment may comprise a system that includes a first node employing a first cache coherency protocol. A detector associated with the first node detects a condition based on responses provided by the first node to requests provided according to a second cache coherency protocol, the second cache coherency protocol being different from the first cache coherency protocol. The first node provides a response to a given one of the requests to the first node that varies based on the condition detected by the detector.
摘要翻译： 公开了用于为不同的高速缓存一致性协议提供响应的系统和方法。 一个实施例可以包括包括采用第一高速缓存一致性协议的第一节点的系统。 与第一节点相关联的检测器基于由第一节点向根据第二高速缓存一致性协议提供的请求提供的响应来检测条件，第二高速缓存一致性协议不同于第一高速缓存一致性协议。 第一节点提供对根据检测器检测到的条件而变化的对第一节点的给定一个请求的响应。
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公开(公告)号：US06961825B2
公开(公告)日：2005-11-01
申请号：US09768418
申请日：2001-01-24
CPC分类号： H04L67/2804 , G06F12/0824 , G06F12/0826 , H04L67/2852 , H04L69/329
摘要： A distributed processing system includes a cache coherency mechanism that essentially encodes network routing information into sectored presence bits. The mechanism organizes the sectored presence bits as one or more arbitration masks that system switches decode and use directly to route invalidate messages through one or more higher levels of the system. The lower level or levels of the system use local routing mechanisms, such as local directories, to direct the invalidate messages to the individual processors that are holding the data of interest.
摘要翻译： 分布式处理系统包括高速缓存一致性机制，其基本上将网络路由信息编码为扇区存在位。 该机制将分区存在位组织为一个或多个仲裁掩码，系统交换机直接解码并使用，以通过系统的一个或多个更高级别路由无效消息。 系统的较低级别或级别使用本地路由机制（如本地目录）将无效消息引导到保存感兴趣的数据的各个处理器。
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36.发明授权Method and apparatus for employing commit-signals and prefetching to maintain inter-reference ordering in a high-performance I/O processor 失效用于采用提交信号和预取以在高性能I / O处理器中维持参考间排序的方法和装置
公开(公告)号：US6085263A
公开(公告)日：2000-07-04
申请号：US956861
申请日：1997-10-24
申请人： Madhumitra Sharma , Chester Pawlowski , Kourosh Gharachorloo , Stephen R. Van Doren , Simon C. Steely, Jr.
发明人： Madhumitra Sharma , Chester Pawlowski , Kourosh Gharachorloo , Stephen R. Van Doren , Simon C. Steely, Jr.
CPC分类号： G06F12/082 , G06F13/124 , G06F12/0862 , G06F2212/621
摘要： An improved I/O processor (IOP) delivers high I/O performance while maintaining inter-reference ordering among memory reference operations issued by an I/O device as specified by a consistency model in a shared memory multiprocessor system. The IOP comprises a retire controller which imposes inter-reference ordering among the operations based on receipt of a commit signal for each operation, wherein the commit signal for a memory reference operation indicates the apparent completion of the operation rather than actual completion of the operation. In addition, the IOP comprises a prefetch controller coupled to an I/O cache for prefetching data into cache without any ordering constraints (or out-of-order). The ordered retirement functions of the IOP are separated from its prefetching operations, which enables the latter operations to be performed in an arbitrary manner so as to improve the overall performance of the system.
摘要翻译： 改进的I / O处理器（IOP）提供高I / O性能，同时在由共享存储器多处理器系统中的一致性模型指定的I / O设备发出的存储器参考操作之间保持参考间排序。 IOP包括退出控制器，其基于对每个操作的提交信号的接收，在操作之间施加参考间排序，其中用于存储器参考操作的提交信号指示操作的明显完成，而不是实际完成操作。 此外，IOP包括耦合到I / O缓存的预取控制器，用于将数据预取到高速缓存中，而没有任何排序限制（或无序）。 IOP的有序退休功能与其预取操作分离，这使得后面的操作能够以任意方式执行，从而提高系统的整体性能。
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公开(公告)号：US5953747A
公开(公告)日：1999-09-14
申请号：US668316
申请日：1996-06-26
CPC分类号： G06F12/0864 , G06F2212/6082
摘要： A prediction mechanism for improving direct-mapped cache performance is shown to include a direct-mapped cache, partitioned into a plurality of pseudo-banks. Prediction means are employed to provide a prediction index which is appended to the cache index to provide the entire address for addressing the direct mapped cache. One embodiment of the prediction means includes a prediction cache which is advantageously larger than the pseudo-banks of the direct-mapped cache and is used to store the prediction index for each cache location. A second embodiment includes a plurality of partial tag stores, each including a predetermined number of tag bits for the data in each bank. A comparison of the tags generates a match in one of the plurality of tag stores, and is used in turn to generate a prediction index. A third embodiment for use with a direct mapped cache divided into two partitions includes a distinguishing bit ram, which is used to provide the bit number of any bit which differs between the tags at the same location in the different banks. The bit number is used in conjunction with a complement signal to provide the prediction index for addressing the direct-mapped cache.
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38.发明授权Method and apparatus for achieving non-inclusive cache performance with inclusive caches 有权用于通过包含缓存实现非包容性缓存性能的方法和装置公开(公告)号：US08769209B2
公开(公告)日：2014-07-01
申请号：US12973051
申请日：2010-12-20
IPC分类号： G06F12/12
CPC分类号： G06F12/0813 , G06F12/128
摘要： An apparatus and method for improving cache performance in a computer system having a multi-level cache hierarchy. For example, one embodiment of a method comprises: selecting a first line in a cache at level N for potential eviction; querying a cache at level M in the hierarchy to determine whether the first cache line is resident in the cache at level M, wherein M
摘要翻译： 一种用于在具有多级高速缓存层级的计算机系统中提高高速缓存性能的装置和方法。 例如，方法的一个实施例包括：在级别N的高速缓存中选择潜在驱逐的第一行; 查询层级中的级别M的高速缓存，以确定第一高速缓存行是否驻留在级别M的高速缓存中，其中M
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公开(公告)号：US08090914B2
公开(公告)日：2012-01-03
申请号：US10760652
申请日：2004-01-20
IPC分类号： G06F12/00
CPC分类号： G06F12/0831 , G06F12/0828 , G06F2212/2542
摘要： A system comprises a first node operative to provide a source broadcast requesting data. The first node associates an F-state with a copy of the data in response to receiving the copy of the data from memory and receiving non-data responses from other nodes in the system. The non-data responses include an indication that at least a second node includes a shared copy of the data. The F-state enabling the first node to serve as an ordering point in the system capable of responding to requests from other nodes in the system with a shared copy of the data.
摘要翻译： 系统包括用于提供源广播请求数据的第一节点。 响应于从存储器接收数据的副本并从系统中的其他节点接收非数据响应，第一节点将F状态与数据的副本相关联。 非数据响应包括至少第二节点包括数据的共享副本的指示。 F状态使得第一节点能够用作系统中能够利用数据的共享副本响应来自系统中其他节点的请求的系统中的订购点。
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公开(公告)号：US07769959B2
公开(公告)日：2010-08-03
申请号：US10760599
申请日：2004-01-20
IPC分类号： G06F13/00
CPC分类号： G06F12/0831
摘要： A system may comprise a first node that includes an ordering point for data, the first node being operative to employ a write-back transaction associated with writing the data back to memory. The first node broadcasts a write-back message to at least one other node in the system in response to an acknowledgement provided by the memory indicating that the ordering point for the data has migrated from the first node to the memory.
摘要翻译： 系统可以包括包括数据的排序点的第一节点，第一节点可操作地采用与将数据写回到存储器相关联的回写事务。 第一节点响应于由存储器提供的确认指示数据的排序点已经从第一节点迁移到存储器的系统中的至少一个其他节点广播回写消息。
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