公开(公告)号：US20080251903A1

公开(公告)日：2008-10-16

申请号：US11735762

申请日：2007-04-16

申请人： Ralf Otremba ,  Xaver Schloegel ,  Klaus Schiess ,  Charlie Tan Tien Lai

发明人： Ralf Otremba ,  Xaver Schloegel ,  Klaus Schiess ,  Charlie Tan Tien Lai

IPC分类号： H01L23/02 ,  H01L21/00

CPC分类号： H01L23/5389 ,  H01L23/142 ,  H01L24/19 ,  H01L24/24 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/20 ,  H01L2224/24227 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/12041 ,  H01L2924/12044 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2224/82 ,  H01L2224/83

摘要： A module having a semiconductor chip with a first contact element on a first main surface and a second contact element on a second main surface is disclosed. The semiconductor chip is arranged on a carrier. An insulating layer and a wiring layer cover the second main surface and the carrier.

摘要翻译： 公开了一种具有在第一主表面上具有第一接触元件的半导体芯片和在第二主表面上的第二接触元件的模块。 半导体芯片布置在载体上。 绝缘层和布线层覆盖第二主表面和载体。

公开(公告)号：US20090042337A1

公开(公告)日：2009-02-12

申请号：US11837087

申请日：2007-08-10

申请人： Stefan Landau ,  Alexander Koenigsberger ,  Joachim Mahler ,  Klaus Schiess

发明人： Stefan Landau ,  Alexander Koenigsberger ,  Joachim Mahler ,  Klaus Schiess

IPC分类号： H01L21/00

CPC分类号： H01L25/072 ,  H01L24/97 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16245 ,  H01L2224/40245 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/01327 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05599

摘要： A method includes providing an integral array of first carriers, arranging first semiconductor chips on the first carriers, and arranging an integral array of second carriers over the semiconductor chips.

摘要翻译： 一种方法包括提供第一载体的整体阵列，在第一载流子上布置第一半导体芯片，以及在半导体芯片上布置第二载流子的整体阵列。

公开(公告)号：US20120112105A1

公开(公告)日：2012-05-10

申请号：US13275488

申请日：2011-10-18

申请人： Harald Burkart ,  Wolfram Maiwald ,  Rolf Hermann ,  Frank Zelano ,  Ralf Heingl ,  Klaus Schiess

发明人： Harald Burkart ,  Wolfram Maiwald ,  Rolf Hermann ,  Frank Zelano ,  Ralf Heingl ,  Klaus Schiess

IPC分类号： F16K31/02

CPC分类号： F02M63/0021 ,  F02M63/0036 ,  F02M63/0052 ,  F02M63/0071 ,  F02M63/0077 ,  F02M63/025 ,  F02M2200/02 ,  F02M2200/04 ,  F16K31/0665

摘要： High-pressure regulating valve (1) with a valve body (2) with an inlet (20) and an outlet (21), a sealing element (4), which acts on a valve seat (3), which is disposed on the valve body (2) between inlet (20) and outlet (21) and has a valve bore (30), an activating element (5) that is mounted able to move along a longitudinal axis and can be activated by an appropriately configured electromagnet (6), wherein an armature (62) of the electromagnet (6) and the activating element (5) are configured as nonconnected, separate structural elements.

摘要翻译： 具有带有入口（20）和出口（21）的阀体（2）的高压调节阀（1），作用在阀座（3）上的密封元件（4） 阀体（2）在入口（20）和出口（21）之间，并具有阀孔（30），启动元件（5），其安装成能够沿着纵向轴线移动并且可由适当配置的电磁体 6），其中电磁体（6）和激活元件（5）的电枢（62）被构造为不连接的分离的结构元件。

公开(公告)号：US08129225B2

公开(公告)日：2012-03-06

申请号：US11837087

申请日：2007-08-10

申请人： Stefan Landau ,  Alexander Koenigsberger ,  Joachim Mahler ,  Klaus Schiess

发明人： Stefan Landau ,  Alexander Koenigsberger ,  Joachim Mahler ,  Klaus Schiess

IPC分类号： H01L21/00

CPC分类号： H01L25/072 ,  H01L24/97 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16245 ,  H01L2224/40245 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/01327 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05599

摘要： A method includes providing an integral array of first carriers, arranging first semiconductor chips on the first carriers, and arranging an integral array of second carriers over the semiconductor chips.

摘要翻译： 一种方法包括提供第一载体的整体阵列，在第一载流子上布置第一半导体芯片，以及在半导体芯片上布置第二载流子的整体阵列。

公开(公告)号：US07956446B2

公开(公告)日：2011-06-07

申请号：US12119665

申请日：2008-05-13

申请人： Alexander Heinrich ,  Klaus Schiess ,  Joachim Mahler

发明人： Alexander Heinrich ,  Klaus Schiess ,  Joachim Mahler

IPC分类号： H01L23/495

CPC分类号： H01L24/40 ,  H01L24/29 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/40095 ,  H01L2224/40247 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73221 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/83825 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01068 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/0781 ,  H01L2924/14 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/37099

摘要： A chip carrier includes first, second and third layers with the second layer situated between the first and third layers. The first and third layers are formed of a first material and the second layer is formed of a second material. The second layer has a plurality of holes extending therethrough and the first material fills the holes.

摘要翻译： 芯片载体包括第一层，第二层和第三层，第二层位于第一层和第三层之间。 第一和第三层由第一材料形成，第二层由第二材料形成。 第二层具有贯穿其中的多个孔，第一材料填充孔。

公开(公告)号：US07701054B2

公开(公告)日：2010-04-20

申请号：US11673929

申请日：2007-02-12

申请人： Thilo Stolze ,  Klaus Schiess ,  Peter Kanschat

发明人： Thilo Stolze ,  Klaus Schiess ,  Peter Kanschat

IPC分类号： H01L23/10

CPC分类号： H01L25/072 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/00

摘要： A power semiconductor module 3 for mounting on a cooling element 4 has at least one substrate 2, on which one or more components 5, 6, 7 are mounted and a module housing 40. The module housing 40 surrounds at least partially the at least one substrate 2. The module housing 40 has opposite sides with a first side facing the cooling element 4, and a second side 42 having one or more openings and a surface turned away from the power semiconductor module 3. Each of the one or more openings has a border, which is sealed by an internal contact 16, 17, 18, 27, 28, which is electrically connected to the one or more components 5, 6, 7. The internal contact protrudes the module housing 40, such that the internal contact not extends beyond said surface of the second side 42 of the module housing 40.

摘要翻译： 用于安装在冷却元件4上的功率半导体模块3具有至少一个基板2，其上安装有一个或多个部件5,6,7和模块壳体40.模块壳体40至少部分地包围至少一个 模块壳体40具有相对的侧面，其具有面对冷却元件4的第一侧，以及具有一个或多个开口的第二侧42和远离功率半导体模块3的表面。所述一个或多个开口中的每一个具有 该边界由电连接到一个或多个部件5,6,7的内部接触件16,17,18,27,28密封。内部触头突出模块壳体40，使得内部触点 不延伸超过模块壳体40的第二侧42的所述表面。

公开(公告)号：US20080191340A1

公开(公告)日：2008-08-14

申请号：US11673929

申请日：2007-02-12

申请人： Thilo Stolze ,  Klaus Schiess ,  Peter Kanschat

发明人： Thilo Stolze ,  Klaus Schiess ,  Peter Kanschat

IPC分类号： H01L23/34 ,  H01L21/00 ,  H01L23/495

CPC分类号： H01L25/072 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/00

摘要： A power semiconductor module 3 for mounting on a cooling element 4 has at least one substrate 2, on which one or more components 5, 6, 7 are mounted and a module housing 40. The module housing 40 surrounds at least partially the at least one substrate 2. The module housing 40 has opposite sides with a first side facing the cooling element 4, and a second side 42 having one or more openings and a surface turned away from the power semiconductor module 3. Each of the one or more openings has a border, which is sealed by an internal contact 16, 17, 18, 27, 28, which is electrically connected to the one or more components 5, 6, 7. The internal contact protrudes the module housing 40, such that the internal contact not extends beyond said surface of the second side 42 of the module housing 40.

摘要翻译： 用于安装在冷却元件4上的功率半导体模块3具有至少一个基板2，其上安装有一个或多个部件5,6,7和模块壳体40.模块壳体40至少部分地包围至少一个 模块壳体40具有相对的侧面，其具有面对冷却元件4的第一侧，以及具有一个或多个开口的第二侧42和远离功率半导体模块3的表面。所述一个或多个开口中的每一个具有 该边界由电连接到一个或多个部件5,6,7的内部接触件16,17,18,27,28密封。内部触头突出模块壳体40，使得内部触点 不延伸超过模块壳体40的第二侧42的所述表面。

公开(公告)号：US20090093090A1

公开(公告)日：2009-04-09

申请号：US11867329

申请日：2007-10-04

申请人： Henrik Ewe ,  Stefan Landau ,  Klaus Schiess ,  Robert Bergmann ,  Alvin Wee Beng Tatt ,  Soon Lock Goh ,  Joachim Mahler ,  Boris Plikat ,  Reimund Engl

发明人： Henrik Ewe ,  Stefan Landau ,  Klaus Schiess ,  Robert Bergmann ,  Alvin Wee Beng Tatt ,  Soon Lock Goh ,  Joachim Mahler ,  Boris Plikat ,  Reimund Engl

IPC分类号： H01L21/56

CPC分类号： H01L23/3107 ,  H01L23/49524 ,  H01L23/49548 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/24 ,  H01L24/80 ,  H01L24/82 ,  H01L2224/24051 ,  H01L2224/24226 ,  H01L2224/24246 ,  H01L2224/24998 ,  H01L2224/32245 ,  H01L2224/76155 ,  H01L2224/82007 ,  H01L2224/82039 ,  H01L2224/82102 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01016 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/351 ,  H01L2924/00

摘要： A method for producing a power semiconductor module having surface mountable flat external contact areas is disclosed. At least one power semiconductor chip is fixed by its rear side on a drain external contact. An insulation layer covers the top side over the side edges of the semiconductor chip as far as the inner housing plane was a leaving free the source and gate contact areas on the top side of the semiconductor chip and also was partly leaving free the top sides of the corresponding external contacts.

摘要翻译： 公开了一种具有表面安装平坦的外部接触区域的功率半导体模块的制造方法。 至少一个功率半导体芯片由其后侧固定在漏极外部触点上。 绝缘层覆盖半导体芯片的侧边缘上方的顶侧，只要内壳平面离开半导体芯片的顶侧上的源极和栅极接触区域，并且还部分地释放出半导体芯片的顶侧 相应的外部联系人。

公开(公告)号：US07479691B2

公开(公告)日：2009-01-20

申请号：US11376871

申请日：2006-03-16

申请人： Henrik Ewe ,  Stefan Landau ,  Klaus Schiess ,  Robert Bergmann

发明人： Henrik Ewe ,  Stefan Landau ,  Klaus Schiess ,  Robert Bergmann

IPC分类号： H01L23/495

CPC分类号： H01L23/49562 ,  H01L23/49524 ,  H01L23/49844 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/82 ,  H01L2224/24051 ,  H01L2224/24226 ,  H01L2224/82039 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/351 ,  H01L2924/00

摘要： A power semiconductor module having surface-mountable flat external contact areas and a method for producing the same is disclosed. In one embodiment, the top sides of the external contacts form an inner housing plane, on which at least one power semiconductor chip is fixed by its rear side on a drain external contact. An insulation layer covers the top side over the edge sides of the semiconductor chip as far as the inner housing plane whilst leaving free the source and gate contact areas on the top side of the semiconductor chip and also whilst partly leaving free the top sides of the corresponding external contacts. Arranged on the insulation layer is a connecting conductive layer between the source contact areas on the top side of the semiconductor chip and the top sides of the source external contacts, and also a gate connecting layer from the gate contact areas to the top side of the gate external contact.

摘要翻译： 公开了一种具有表面安装平坦的外部接触区域的功率半导体模块及其制造方法。 在一个实施例中，外部接触件的顶侧形成内部壳体平面，其上至少一个功率半导体芯片由其后侧固定在排水外部接触件上。 绝缘层覆盖半导体芯片的边缘侧的顶侧至内部壳体平面，同时在半导体芯片的顶侧上释放源极和栅极接触区域，并且同时部分地释放半导体芯片的顶侧 相应的外部联系人。 在绝缘层上排列的是在半导体芯片的上侧的源极接触区域和源极外部接触件的顶侧之间的连接导电层，以及从栅极接触区域到顶部侧的栅极连接层 门外部接触。

公开(公告)号：US20070200250A1

公开(公告)日：2007-08-30

申请号：US11678960

申请日：2007-02-26

申请人： Alexander Koenigsberger ,  Klaus Schiess

发明人： Alexander Koenigsberger ,  Klaus Schiess

IPC分类号： H01L23/48

CPC分类号： H01L24/34 ,  H01L23/49562 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16245 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01068 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/37099 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A semiconductor device using lead technology includes a semiconductor chip with external side electrodes of semiconductor components disposed on its top side. On its rear side, the semiconductor chip is connected to a rear side internal lead adapted to the rear side of semiconductor chip. On its top side, the semiconductor chip is connected a plurality of top side internal leads. The top side internal leads are electrically connected to external leads of the semiconductor device.

摘要翻译： 使用引线技术的半导体器件包括半导体芯片，半导体元件的外侧电极设置在其顶侧。 在其后侧，半导体芯片连接到适于半导体芯片的后侧的后侧内部引线。 在其顶侧，半导体芯片连接有多个顶侧内部引线。 顶侧内部引线电连接到半导体器件的外部引线。