公开(公告)号：US06481000B1

公开(公告)日：2002-11-12

申请号：US09608061

申请日：2000-06-29

申请人： Ketan Zaveri ,  Christopher F. Lane ,  Srinivas T. Reddy ,  Andy L. Lee ,  Cameron R. McClintock ,  Bruce B. Pedersen

发明人： Ketan Zaveri ,  Christopher F. Lane ,  Srinivas T. Reddy ,  Andy L. Lee ,  Cameron R. McClintock ,  Bruce B. Pedersen

IPC分类号： G06F1750

CPC分类号： G01R31/318516

摘要： A programmable logic device is provided that contains circuitry that may be used for observing logic signals from programmable logic circuits on the device for testing the operation of the device. Circuitry is also provided that may be used for preloading data into various circuits on the device. The logic signal observing circuitry may allow registered signals to be observed, may allow combinatorial signals to be observed, or may allow both registered and combinatorial signals to be observed.

摘要翻译： 提供了一种可编程逻辑器件，其包含电路，该电路可用于观察器件上来自可编程逻辑电路的逻辑信号，以测试器件的操作。 还提供了可用于将数据预加载到设备上的各种电路中的电路。 逻辑信号观察电路可以允许观察注册的信号，可以允许观察组合信号，或者允许观察到注册信号和组合信号。

公开(公告)号：US06344755B1

公开(公告)日：2002-02-05

申请号：US09691424

申请日：2000-10-18

申请人： Srinivas T. Reddy ,  Manuel Mejia ,  Andy L. Lee ,  Bruce B. Pedersen

发明人： Srinivas T. Reddy ,  Manuel Mejia ,  Andy L. Lee ,  Bruce B. Pedersen

IPC分类号： H03K19003

CPC分类号： H03K19/17764 ,  H03K19/17736

摘要： A programmable logic device is provided that allows a redundant row of programmable logic to be shifted into place to repair the device when a defect is detected in a row of programmable logic on the device. The redundant row is shifted into place by routing programming data into the normal logic and the redundant logic while bypassing the row of logic containing the defect. Switching circuitry may be used to direct programming data into the serial inputs of various data registers that are then used to load the programming data into the device. The patterns of programmable connections that are made between programmable logic regions on the device and vertical and horizontal conductors also allow redundant logic to be shifted into place. Some connections between the logic and the horizontal and vertical conductors may be identical within a column to facilitate shifting. Other connections may only partially overlap between respective rows. The partially overlapping pattern allows the connections to be less regular, which increases flexibility when routing signals on the device.

摘要翻译： 提供了一种可编程逻辑器件，其允许在器件上的可编程逻辑行中检测到缺陷时将冗余的可编程逻辑行移位到位以修复器件。 通过将编程数据路由到正常逻辑和冗余逻辑中来绕过包含缺陷的逻辑行，将冗余行移位到位。 开关电路可用于将编程数据引导到各种数据寄存器的串行输入，然后将其用于将编程数据加载到器件中。 在设备上的可编程逻辑区域和垂直和水平导体之间进行的可编程连接的模式也允许将冗余逻辑移位到位。 逻辑和水平和垂直导体之间的一些连接可以在列内相同以便于移动。 其他连接可能仅在相应行之间部分重叠。 部分重叠的模式允许连接不太规则，这在设备上路由信号时增加灵活性。

公开(公告)号：US06201404B1

公开(公告)日：2001-03-13

申请号：US09295672

申请日：1999-04-20

申请人： Srinivas T. Reddy ,  Manuel Mejia ,  Andy L. Lee ,  Bruce B. Pedersen

发明人： Srinivas T. Reddy ,  Manuel Mejia ,  Andy L. Lee ,  Bruce B. Pedersen

IPC分类号： H03K19003

CPC分类号： H03K19/17764 ,  H03K19/17736

摘要： A programmable logic device is provided that allows a redundant row of programmable logic to be shifted into place to repair the device when a defect is detected in a row of programmable logic on the device. The redundant row is shifted into place by routing programming data into the normal logic and the redundant logic while bypassing the row of logic containing the defect. Switching circuitry may be used to direct programming data into the serial inputs of various data registers that are then used to load the programming data into the device. The patterns of programmable connections that are made between programmable logic regions on the device and vertical and horizontal conductors also allow redundant logic to be shifted into place. Some connections between the logic and the horizontal and vertical conductors may be identical within a column to facilitate shifting. Other connections may only partially overlap between respective rows. The partially overlapping pattern allows the connections to be less regular, which increases flexibility when routing signals on the device.

摘要翻译： 提供了一种可编程逻辑器件，其允许在器件上的可编程逻辑行中检测到缺陷时将冗余的可编程逻辑行移位到位以修复器件。 通过将编程数据路由到正常逻辑和冗余逻辑中来绕过包含缺陷的逻辑行，将冗余行移位到位。 开关电路可用于将编程数据引导到各种数据寄存器的串行输入，然后将其用于将编程数据加载到器件中。 在设备上的可编程逻辑区域和垂直和水平导体之间进行的可编程连接的模式也允许将冗余逻辑移位到位。 逻辑和水平和垂直导体之间的一些连接可以在列内相同以便于移动。 其他连接可能仅在相应行之间部分重叠。 部分重叠的模式允许连接不太规则，这在设备上路由信号时增加灵活性。

公开(公告)号：US08461869B1

公开(公告)日：2013-06-11

申请号：US13214147

申请日：2011-08-19

申请人： Irfan Rahim ,  Andy L. Lee ,  Bruce B. Pedersen ,  Jeffrey T. Watt ,  Mao Du ,  Richard G. Cliff

发明人： Irfan Rahim ,  Andy L. Lee ,  Bruce B. Pedersen ,  Jeffrey T. Watt ,  Mao Du ,  Richard G. Cliff

IPC分类号： H03K19/003

CPC分类号： H03K19/003 ,  H03K19/17784

摘要： An apparatus includes a temperature sensor, a voltage regulator, and a field programmable gate array (FPGA). The temperature sensor and the voltage regulator are adapted, respectively, to provide a temperature signal, and to provide at least one output voltage. The FPGA includes at least one circuit adapted to receive the at least one output voltage of the voltage regulator, and a set of monitor circuits adapted to provide indications of process and temperature for the at least one circuit. The FPGA further includes a controller adapted to derive a body-bias signal and a voltage-level signal from the temperature signal, from the indications of process and temperature for the at least one circuit, and from the at least one output voltage of the voltage regulator. The controller is further adapted to provide the body-bias signal to at least one transistor in the at least one circuit, and to provide the voltage-level signal to the voltage regulator.

摘要翻译： 一种装置包括温度传感器，电压调节器和现场可编程门阵列（FPGA）。 温度传感器和电压调节器分别适于提供温度信号，并提供至少一个输出电压。 FPGA包括适于接收电压调节器的至少一个输出电压的至少一个电路，以及适于提供至少一个电路的过程和温度指示的一组监视器电路。 FPGA还包括控制器，其适于从温度信号，从至少一个电路的处理和温度指示以及电压的至少一个输出电压导出体偏置信号和电压电平信号 调节器 所述控制器还适于将所述体偏置信号提供给所述至少一个电路中的至少一个晶体管，并且向所述电压调节器提供所述电压电平信号。

公开(公告)号：US5376844A

公开(公告)日：1994-12-27

申请号：US39944

申请日：1993-03-29

申请人： Bruce B. Pedersen ,  Richard G. Cliff ,  Bahram Ahanin ,  Craig S. Lytle ,  Francis B. Heile ,  Kerry S. Veenstra

发明人： Bruce B. Pedersen ,  Richard G. Cliff ,  Bahram Ahanin ,  Craig S. Lytle ,  Francis B. Heile ,  Kerry S. Veenstra

IPC分类号： H01L21/82 ,  H03K19/173 ,  H03K19/177

CPC分类号： H03K19/1737 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/17736

摘要： A programmable logic array integrated circuit has a plurality of programmable logic elements grouped into a plurality of mutually exclusive groups. Each group includes signal conductors uniquely associated with that group for conveying signals between the programmable logic elements in that group. Other signal conductors are provided for conveying signals between the groups. Multiplexers can be used in various ways to reduce the number of programmable interconnections required between signal conductors.

摘要翻译： 可编程逻辑阵列集成电路具有被分组成多个相互排斥的组的多个可编程逻辑元件。 每个组包括与该组唯一相关联的信号导体，用于在该组中的可编程逻辑元件之间传送信号。 提供其他信号导体用于在组之间传送信号。 多路复用器可以以各种方式用于减少信号导体之间所需的可编程互连数量。

公开(公告)号：US5485103A

公开(公告)日：1996-01-16

申请号：US356516

申请日：1994-12-15

申请人： Bruce B. Pedersen ,  Richard G. Cliff ,  Bahram Ahanin ,  Craig S. Lytle ,  Francis B. Heile ,  Kerry S. Veenstra

发明人： Bruce B. Pedersen ,  Richard G. Cliff ,  Bahram Ahanin ,  Craig S. Lytle ,  Francis B. Heile ,  Kerry S. Veenstra

IPC分类号： H01L21/82 ,  H03K19/173 ,  H03K19/177

CPC分类号： H03K19/1737 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/17736

摘要： A programmable logic array integrated circuit has a plurality of programmable logic elements grouped into a plurality of mutually exclusive groups. Each group includes signal conductors uniquely associated with that group for conveying signals between the programmable logic elements in that group. Other signal conductors are provided for conveying signals between the groups. Multiplexers can be used in various ways to reduce the number of programmable interconnections required between signal conductors.

摘要翻译： 可编程逻辑阵列集成电路具有被分组成多个相互排斥的组的多个可编程逻辑元件。 每个组包括与该组唯一相关联的信号导体，用于在该组中的可编程逻辑元件之间传送信号。 提供其他信号导体用于在组之间传送信号。 多路复用器可以以各种方式用于减少信号导体之间所需的可编程互连数量。

公开(公告)号：US5436575A

公开(公告)日：1995-07-25

申请号：US111693

申请日：1993-08-25

申请人： Bruce B. Pedersen ,  Richard G. Cliff ,  Bahram Ahanin ,  Craig S. Lytle ,  Francis B. Heile ,  Kerry S. Veenstra

发明人： Bruce B. Pedersen ,  Richard G. Cliff ,  Bahram Ahanin ,  Craig S. Lytle ,  Francis B. Heile ,  Kerry S. Veenstra

IPC分类号： G11C8/12 ,  H03K19/173 ,  H03K19/177

CPC分类号： H03K19/17736 ,  G11C8/12 ,  H03K19/1737 ,  H03K19/17704

摘要： A programmable logic array integrated circuit has a number of programmable logic modules which are grouped together in a plurality of logic array blocks ("LABs"). The LABs are arranged on the circuit in a two dimensional array. A conductor network is provided for interconnecting any logic module with any other logic module. In addition, adjacent or nearby logic modules are connectable to one another for such special purposes as providing a carry chain between logic modules and/or for connecting two or more modules together to provide more complex logic functions without having to make use of the general interconnection network. Another network of so-called fast or universal conductors is provided for distributing widely used logic signals such as clock and clear signals throughout the circuit. Multiplexers can be used in various ways to reduce the number of programmable interconnections required between signal conductors.

公开(公告)号：US06759870B2

公开(公告)日：2004-07-06

申请号：US10372373

申请日：2003-02-20

申请人： Richard G. Cliff ,  Bahram Ahanin ,  Craig Schilling Lytle ,  Francis B. Heile ,  Bruce B. Pedersen ,  Kerry Veenstra

发明人： Richard G. Cliff ,  Bahram Ahanin ,  Craig Schilling Lytle ,  Francis B. Heile ,  Bruce B. Pedersen ,  Kerry Veenstra

IPC分类号： H03K19177

CPC分类号： H03K19/17736 ,  G01R31/318516 ,  G11C8/12 ,  H03K19/1737 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/17792

摘要： A programmable logic array integrated circuit has a number of programmable logic modules which are grouped together in a plurality of logic array blocks (“LABs”). The LABs are arranged on the circuit in a two dimensional array. A conductor network is provided for interconnecting any logic module with any other logic module. In addition, adjacent or nearby logic modules are connectable to one another for such special purposes as providing a carry chain between logic modules and/or for connecting two or more modules together to provide more complex logic functions without having to make use of the general interconnection network. Another network of so-called fast or universal conductors is provided for distributing widely used logic signals such as clock and clear signals throughout the circuit. Multiplexers can be used in various ways to reduce the number of programmable interconnections required between signal conductors.

公开(公告)号：US06259272B1

公开(公告)日：2001-07-10

申请号：US09328704

申请日：1999-06-09

申请人： Richard G. Cliff ,  Francis B. Heile ,  Chiakang Sung ,  Bonnie I. Wang ,  Bruce B. Pedersen

发明人： Richard G. Cliff ,  Francis B. Heile ,  Chiakang Sung ,  Bonnie I. Wang ,  Bruce B. Pedersen

IPC分类号： H01L2500

CPC分类号： H03K19/1736 ,  H03K19/1737 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/17744 ,  H03K19/1776

摘要： A programmable logic array integrated circuit device has a plurality of regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of regions. The output signals of several regions share a group of drivers for applying region output signals to interconnection conductors that convey signals between regions. This conserves driver resources and increases signal routing flexibility. Various approaches can be used for configuring the interconnection conductors to also conserve interconnection conductor resources. Logic regions may be used to directly drive specific input/output cells, thereby simplifying signal routing to the I/O cells and also possibly simplifying the structure of the I/O cells (e.g., by allowing certain I/O cell functions to be performed in the associated logic region). Region output signal routing flexibility may also be enhanced to facilitate simultaneous performance of combinatorial logic and a separate “lonely register” function in modules of the regions.

公开(公告)号：US5260611A

公开(公告)日：1993-11-09

申请号：US880942

申请日：1992-05-08

申请人： Richard G. Cliff ,  Bahram Ahanin ,  Craig S. Lytle ,  Francis B. Heile ,  Bruce B. Pedersen ,  Kerry Veenstra

发明人： Richard G. Cliff ,  Bahram Ahanin ,  Craig S. Lytle ,  Francis B. Heile ,  Bruce B. Pedersen ,  Kerry Veenstra

IPC分类号： H01L21/82 ,  H03K19/0175 ,  H03K19/173 ,  H03K19/177

CPC分类号： H03K19/17736 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/1774 ,  H03K19/17792

摘要： A programmable logic array integrated circuit has a number of programmable logic modules which are grouped together in a plurality of logic array blocks ("LABs"). The LABs are arranged on the circuit in a two dimensional array. A conductor network is provided for interconnecting any logic module with any other logic module. In addition, adjacent or nearby logic modules are connectable to one another for such special purposes as providing a carry chain between logic modules and/or for connecting two or more modules together to provide more complex logic functions without having to make use of the general interconnection network. Another network of so-called fast or universal conductors is provided for distributing widely used logic signals such as clock and clear signals throughout the circuit.

摘要翻译： 可编程逻辑阵列集成电路具有多个可编程逻辑模块，它们被组合在多个逻辑阵列块（“LAB”）中。 LAB以二维阵列布置在电路上。 提供一个导线网络，用于将任何逻辑模块与任何其他逻辑模块相互连接。 此外，相邻或附近的逻辑模块可以彼此连接，用于在逻辑模块之间提供进位链和/或用于将两个或多个模块连接在一起以提供更复杂的逻辑功能而不必利用一般互连的特殊目的 网络。 提供了所谓的快速或通用导体的另一网络，用于在整个电路中分布广泛使用的逻辑信号，例如时钟和清除信号。