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31.发明授权Data processor having capability to perform both floating point operations and memory access in response to a single instruction 失效数据处理器具有响应于单个指令执行浮点运算和存储器访问的能力
公开(公告)号：US5673407A
公开(公告)日：1997-09-30
申请号：US207987
申请日：1994-03-08
申请人： Sydney W. Poland , Christopher J. Read , Karl M. Guttag , Robert J. Gove , Michael Gill , Nicholas Ing Simmons , Erick Oakland , Jeremiah E. Golston
发明人： Sydney W. Poland , Christopher J. Read , Karl M. Guttag , Robert J. Gove , Michael Gill , Nicholas Ing Simmons , Erick Oakland , Jeremiah E. Golston
CPC分类号： G06F5/012 , G06F9/30014 , G06F9/30025 , G06F9/30036 , G06F9/30167 , G06F9/3877
摘要： A data processor includes both integer and floating point operation units and operates as a reduced instruction set computer (RISC). A modification of the normal load/store RISC operations includes within in its instruction set some instructions that permit floating point operations to be paired with load or store operations. These operations include: vector floating point add; vector multiply accumulate; vector floating point multiply; vector multiply subtract; vector reverse subtract; vector round floating point input; vector round integer input; and vector floating point subtract.
摘要翻译： 数据处理器包括整数和浮点运算单元，并作为精简指令集计算机（RISC）运行。 正常加载/存储RISC操作的修改包括在其指令集中的一些允许浮点运算与加载或存储操作配对的指令。 这些操作包括：向量浮点添加; 向量乘积 向量浮点乘法; 矢量乘法; 矢量反向减法; 向量圆浮点输入; 向量圆整数输入; 和向量浮点减法。
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公开(公告)号：US5768609A
公开(公告)日：1998-06-16
申请号：US483657
申请日：1995-06-07
IPC分类号： G06F15/173 , G06F15/80
CPC分类号： G06F15/17375
摘要： There is disclosed a multi-processor system and method arranged, in one embodiment, as an image and graphics processor. The image processor is structured with several individual processors all having communication links to several memories. A crossbar switch serves to establish the processor memory links. The entire image processor, including the individual processors, the crossbar switch and the memories, is contained on a single silicon chip.
摘要翻译： 已经公开了在一个实施例中将图像处理器和图形处理器设置为多处理器系统和方法。 图像处理器被构造成具有几个单独的处理器，它们都具有到几个存储器的通信链路。 交叉开关用于建立处理器存储器链路。 整个图像处理器（包括各个处理器，交叉开关和存储器）都包含在单个硅芯片上。
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33.发明授权Single integrated circuit embodying a dual heterogenous processors with separate instruction handling hardware 失效单一集成电路体现了具有单独指令处理硬件的双异质处理器公开(公告)号：US06948050B1
公开(公告)日：2005-09-20
申请号：US09875136
申请日：2001-06-06
IPC分类号： G06F9/38 , G06F15/16 , G06F15/173
CPC分类号： G06F9/3885 , G06F9/3851 , G06F15/17375
摘要： A single integrated circuit includes first and second data processors operating on different instruction sets independently operating on disjoint programs and data. The single integrated circuit preferably includes an external interface, a shared data transfer controller and shared memory divided into plural independently accessible memory banks. The two data processors are preferably a digital signal processor (DSP) and a reduced instruction set computer (RISC) processor. The DSP and RISC processors are suitably programmed to perform differing aspects of computer image processing.
摘要翻译： 单个集成电路包括在不相交的程序和数据上独立操作的不同指令集上操作的第一和第二数据处理器。 单个集成电路优选地包括外部接口，共享数据传输控制器和被分成多个可独立存取的存储体的共享存储器。 两个数据处理器优选地是数字信号处理器（DSP）和精简指令集计算机（RISC）处理器。 DSP和RISC处理器被适当地编程以执行计算机图像处理的不同方面。
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34.发明授权Unique processor identifier in a multi-processing system having plural memories with a unified address space corresponding to each processor 失效具有多个具有与每个处理器对应的统一地址空间的存储器的多处理系统中的唯一处理器标识符
公开(公告)号：US5696913A
公开(公告)日：1997-12-09
申请号：US472827
申请日：1995-06-07
IPC分类号： G06F15/167 , G06F12/02 , G06F12/06 , G06F15/173 , G06F15/80 , G06F13/00
CPC分类号： G06F15/17375 , G06F12/0284
摘要： A multi-processing system includes a plurality of memories and a plurality of processors. Each of the memories has a unique addressable memory portion of a single memory address space. Each processors has a predetermined plurality of corresponding memories. These corresponding memories have a corresponding base address within said single memory address space The processors generate addresses for read/write access to data stored within said plurality of memories in accordance with received instructions. A switch matrix connected to the memories and the processors responds to an address generated by a processor to selectively route data between that processor and a memories whose unique addressable memory portion encompasses that address. Each processor has a register with a plurality of read only bits which uniquely identify that processor within the multi-processing system. The processor may employ this unique processor identifier to compute the base address corresponding to that processor. This enables programs which may execute independently of the processor within the multi-processing system.
摘要翻译： 多处理系统包括多个存储器和多个处理器。 每个存储器具有单个存储器地址空间的唯一可寻址存储器部分。 每个处理器具有预定的多个对应的存储器。 这些相应的存储器在所述单个存储器地址空间内具有对应的基址。根据接收到的指令，处理器产生用于对存储在所述多个存储器中的数据进行读/写访问的地址。 连接到存储器和处理器的开关矩阵响应由处理器产生的地址，以选择性地在该处理器与其唯一可寻址存储器部分包含该地址的存储器之间路由数据。 每个处理器具有一个具有唯一地识别多处理系统内的处理器的多个只读位的寄存器。 处理器可以采用这种唯一的处理器标识符来计算对应于该处理器的基地址。 这使得能够独立于多处理系统内的处理器执行的程序。
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35.发明授权Single integrated circuit embodying a risc processor and a digital signal processor 失效单个集成电路体现了一个risc处理器和一个数字信号处理器公开(公告)号：US06260088B1
公开(公告)日：2001-07-10
申请号：US09517990
申请日：2000-03-03
IPC分类号： G06F1300
CPC分类号： G06F15/17375
摘要： A single integrated circuit includes first and second data processors operating on different instruction sets independently operating on disjoint programs and data. The single integrated circuit preferably includes an external interface, a shared data transfer controller and shared memory divided into plural independently accessible memory banks. The two data processors are preferably a digital signal processor (DSP) and a reduced instruction set computer (RISC) processor. The DSP and RISC processors are suitably programmed to perform differing aspects of computer image processing.
摘要翻译： 单个集成电路包括在不相交的程序和数据上独立操作的不同指令集上操作的第一和第二数据处理器。 单个集成电路优选地包括外部接口，共享数据传输控制器和被分成多个可独立存取的存储体的共享存储器。 两个数据处理器优选地是数字信号处理器（DSP）和精简指令集计算机（RISC）处理器。 DSP和RISC处理器被适当地编程以执行计算机图像处理的不同方面。
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36.发明授权System and method of memory access in apparatus having plural processors and plural memories 失效具有多个处理器和多个存储器的设备中的存储器访问的系统和方法
公开(公告)号：US6070003A
公开(公告)日：2000-05-30
申请号：US264582
申请日：1994-06-22
IPC分类号： G06F15/173 , G06F13/16
CPC分类号： G06F15/17375
摘要： There is disclosed a multi-processor system and method arranged, in one embodiment, as an image and graphics processor. The image processor is structured with several individual processors all having communication links to several memories. A crossbar switch serves to establish the processor memory links. The entire image processor, including the individual processors, the crossbar switch and the memories, is contained on a single silicon chip.
摘要翻译： 已经公开了在一个实施例中将图像处理器和图形处理器设置为多处理器系统和方法。 图像处理器被构造成具有几个单独的处理器，它们都具有到几个存储器的通信链路。 交叉开关用于建立处理器存储器链路。 整个图像处理器（包括各个处理器，交叉开关和存储器）都包含在单个硅芯片上。
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37.发明授权Brightness and contrast control for a digital pulse-width modulated display system 失效数字脉宽调制显示系统的亮度和对比度控制公开(公告)号：US06362835B1
公开(公告)日：2002-03-26
申请号：US08156541
申请日：1993-11-23
申请人： Paul M. Urbanus , Robert J. Gove
发明人： Paul M. Urbanus , Robert J. Gove
IPC分类号： G09G300
CPC分类号： G09G3/34 , G09G3/20 , G09G3/2022 , G09G3/346 , G09G2320/0606 , G09G2320/0626 , G09G2320/066 , G09G2320/0666
摘要： A method and system for adjusting the brightness and contrast of a digital pulse-width modulated display without scaling the input image data. Brightness is adjusted by changing the duty cycle of a displayed pixel either by altering the bit display durations, or by turning the pixel on during blanking periods 36. The contrast ratio may be altered by changing the display duration of at least one of the MSBs differently than the display duration of at least one of the LSBs. Contrast may be increased by extending the MSB display periods 50 and shortening the LSB display periods 52. Contrast may be decreased by shortening the MSB display periods 56 and extending the LSB display periods 58. The color tint of the displayed image may be altered by individually changing the brightness of the constituent colors.
摘要翻译： 一种用于调节数字脉冲宽度调制显示器的亮度和对比度而不缩放输入图像数据的方法和系统。 通过改变比特显示持续时间来改变所显示的像素的占空比，或者通过在消隐期间36期间转动像素来调节亮度。可以通过改变至少一个MSB的显示持续时间来改变对比度 比LSB中的至少一个的显示持续时间长。 可以通过延长MSB显示周期50并缩短LSB显示周期52来增加对比度。可以通过缩短MSB显示周期56并延长LSB显示周期58来减小对比度。可以通过单独地改变显示图像的色调 改变组成颜色的亮度。
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公开(公告)号：US06232936B1
公开(公告)日：2001-05-15
申请号：US08415101
申请日：1995-03-31
IPC分类号： G09G334
CPC分类号： G02B26/0841
摘要： A method and device for increasing the effective horizontal resolution of a display device. One embodiment forms a cardinal array of digital micromirror elements by staggering alternate rows in an array. According to a second embodiment, an ordinal pixel array 57, is converted to a cardinal pixel array, by grouping SLM elements 59, 61, 63, and 65 into a pixel block 58. All of the elements in a pixel block are controlled in unison such that the pixel block acts like a single pixel. Rows of pixel blocks 67 and 69 are offset to provide the effect of a cardinal array of pixels without the decrease in efficiency sometimes associated with cardinal pixel arrays.
摘要翻译： 一种用于增加显示装置的有效水平分辨率的方法和装置。 一个实施例通过交错阵列中的交替行来形成数字微镜元件的基数阵列。 根据第二实施例，通过将SLM元件59,61,63和65分组成像素块58，将序数像素阵列57转换为基本像素阵列。像素块中的所有元素被一致地控制 使得像素块像单个像素那样起作用。 像素块67和69的行被偏移以提供像素阵列的效果，而不会有效地与主要像素阵列相关联的效率的降低。
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公开(公告)号：US5973733A
公开(公告)日：1999-10-26
申请号：US707045
申请日：1996-08-30
申请人： Robert J. Gove
发明人： Robert J. Gove
CPC分类号： H04N5/23264 , H04N5/145 , H04N5/23248 , H04N5/23254 , H04N5/77
摘要： A system (26) for stabilizing a video recording of a scene (20, 22, & 24) made with a video camera (34) is provided. The video recording may include video data (36) and audio (38) data. The system (26) may include source frame storage (64) for storing source video data (36) as a plurality of sequential frames. The system (26) may also include a processor (50) for detecting camera movement occurring during recording and for modifying the video data (36) to compensate for the camera movement. Additionally the system (26) may include destination frame storage (70) for storing the modified video data as plurality of sequential frames.
摘要翻译： 提供一种用于稳定由摄像机（34）制成的场景（20,22，＆24）的视频记录的系统（26）。 视频记录可以包括视频数据（36）和音频（38）数据。 系统（26）可以包括用于将源视频数据（36）存储为多个顺序帧的源帧存储（64）。 系统（26）还可以包括处理器（50），用于检测在记录期间发生的相机移动，并且用于修改视频数据（36）以补偿相机运动。 另外，系统（26）可以包括用于将修改的视频数据存储为多个连续帧的目的地帧存储（70）。
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公开(公告)号：US5748250A
公开(公告)日：1998-05-05
申请号：US533409
申请日：1995-09-25
申请人： Vishal Markandey , Robert J. Gove
发明人： Vishal Markandey , Robert J. Gove
CPC分类号： H04N7/012 , H04N5/145 , H04N5/7458 , H04N2005/7466
摘要： A line generator (31) for receiving fields of pixel data sampled from a video input signal and for generating additional lines of pixel data so that the display frames will have more lines than the fields. The line generator (31) has a motion detector (31a) that determines, on a pixel by pixel basis, whether some part of the current field is in motion. A motion signal from the motion detector (31a) is used to select between outputs of two or more pixel generators (31b, 31c). One of the pixel generators (31b) provides pixel values that are better suited for display when the image is not in motion. The other pixel generator (31c) provides pixel values that are better suited for display when the image is in motion.
摘要翻译： 一种线生成器（31），用于接收从视频输入信号采样的像素数据的场，并产生附加的像素数据行，使得显示帧将具有比场多的行。 线发生器（31）具有运动检测器（31a），该运动检测器（31a）逐像素地确定当前场的某些部分是否运动。 来自运动检测器（31a）的运动信号用于在两个或更多个像素发生器（31b，31c）的输出之间进行选择。 像素发生器（31b）之一提供当图像不运动时更适合于显示的像素值。 另一像素生成器（31c）提供当图像运动时更适合于显示的像素值。
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