Apparatus and method for a security lock
    31.
    发明授权
    Apparatus and method for a security lock 失效
    用于安全锁的装置和方法

    公开(公告)号:US4648639A

    公开(公告)日:1987-03-10

    申请号:US752369

    申请日:1985-07-03

    IPC分类号: E05C1/16 E05B55/10

    摘要: A security lock comprising a latch positioned at the edge of a door which is actuated to selectively lock or unlock the door. The security lock includes an optional key-actuated dead bolt which can provide additional security when needed. A mechanism for locking or unlocking the latch comprises a hand-actuated knob positioned on the inside of the door so that when the dead bolt is not in use, the latch mechanism may still be locked or unlocked simply by rotating the knob between two positions. The mechanism for locking the latch is disengaged when the latch is in the locked position. If the latch is in the locked position when the door is opened, when the door is closed the latch is automatically unlocked to prevent a person from accidentally being locked out.

    摘要翻译: 一种安全锁,其包括位于门的边缘处的闩锁,其被致动以选择性地锁定或解锁门。 安全锁包括可选的钥匙致动止动螺栓,可在需要时提供额外的安全性。 用于锁定或解锁闩锁的机构包括位于门的内部的手动操作的旋钮,使得当不使用止动螺栓时,通过在两个位置之间旋转旋钮,闩锁机构仍然可以被锁定或解锁。 当闩锁处于锁定位置时,锁定闩锁的机构脱开。 如果门打开时闩锁处于锁定位置,当门关闭时,闩锁将自动解锁,以防止人员意外锁定。

    Internal loop-back architecture for parallel serializer/deserializer (SERDES)
    33.
    发明授权
    Internal loop-back architecture for parallel serializer/deserializer (SERDES) 有权
    并行串行器/解串器(SERDES)的内部环回架构

    公开(公告)号:US07742427B2

    公开(公告)日:2010-06-22

    申请号:US12037185

    申请日:2008-02-26

    IPC分类号: H04L12/26

    CPC分类号: H04L25/45 H04L1/243

    摘要: An internal loop-back architecture for a parallel serializer/deserializer (SERDES) includes a transmitter macro including a plurality of transmit elements arranged in a parallel architecture, and a receiver macro including a plurality of receive elements arranged in a parallel architecture, wherein at least a portion of the transmit elements and a portion of the receive elements share a communication channel and wherein any of the plurality of transmit elements in a row can communicate with any of the plurality of receive elements in a row, and wherein each of the plurality of transmit element includes a loop-back arrangement with each of the plurality of receive elements.

    摘要翻译: 用于并行串行器/解串器(SERDES)的内部环回架构包括包括以并行架构布置的多个发送元件的发送器宏,以及包括以并行架构排列的多个接收元件的接收器宏,其中至少 所述发射元件的一部分和所述接收元件的一部分共享通信信道,并且其中一行中的所述多个发射元件中的任一个可以与所述多个接收元件中的任何一个连接,并且其中所述多个 发射元件包括与所述多个接收元件中的每一个的环回布置。

    Internal Loop-Back Architecture For Parallel Serializer/Deserializer (SERDES)
    34.
    发明申请
    Internal Loop-Back Architecture For Parallel Serializer/Deserializer (SERDES) 有权
    并行串行器/解串器(SERDES)的内部环回架构

    公开(公告)号:US20090213913A1

    公开(公告)日:2009-08-27

    申请号:US12037185

    申请日:2008-02-26

    IPC分类号: H04B1/38 H04L5/16

    CPC分类号: H04L25/45 H04L1/243

    摘要: An internal loop-back architecture for a parallel serializer/deserializer (SERDES) includes a transmitter macro including a plurality of transmit elements arranged in a parallel architecture, and a receiver macro including a plurality of receive elements arranged in a parallel architecture, wherein at least a portion of the transmit elements and a portion of the receive elements share a communication channel and wherein any of the plurality of transmit elements in a row can communicate with any of the plurality of receive elements in a row, and wherein each of the plurality of transmit element includes a loop-back arrangement with each of the plurality of receive elements.

    摘要翻译: 用于并行串行器/解串器(SERDES)的内部环回架构包括包括以并行架构布置的多个发送元件的发送器宏,以及包括以并行架构排列的多个接收元件的接收器宏,其中至少 所述发射元件的一部分和所述接收元件的一部分共享通信信道,并且其中一行中的所述多个发射元件中的任一个可以与所述多个接收元件中的任何一个连接,并且其中所述多个 发射元件包括与所述多个接收元件中的每一个的环回布置。

    Generating a device address persistent across different instantiations of an electronic device
    35.
    发明申请
    Generating a device address persistent across different instantiations of an electronic device 审中-公开
    在电子设备的不同实例中生成设备地址

    公开(公告)号:US20070294430A1

    公开(公告)日:2007-12-20

    申请号:US11471211

    申请日:2006-06-20

    IPC分类号: G06F15/16

    CPC分类号: G06F11/006

    摘要: Generating a device address persistent across different instantiations of an electronic device at a computer system. A device identifier identifying the electronic device is received from the electronic device communicatively coupled to the computer system at a interface. An interface identifier identifying the interface is received. A persistent device identifier based on the device identifier and the interface identifier is generated. The persistent device identifier statically defines the electronic device at the interface across different instantiations of the electronic device at the computer system.

    摘要翻译: 在计算机系统的电子设备的不同实例中生成设备地址。 从界面处通信地耦合到计算机系统的电子设备接收识别电子设备的设备标识符。 接收标识接口的接口标识符。 生成基于设备标识符和接口标识符的持久设备标识符。 持久性设备标识符在计算机系统处静态地定义电子设备在电子设备的不同实例的接口处。

    Steer knuckle with integrated cam support

    公开(公告)号:US06612390B2

    公开(公告)日:2003-09-02

    申请号:US09757042

    申请日:2001-01-09

    IPC分类号: B62D718

    摘要: A steer axle for a heavy duty vehicle is provided including an axle assembly having an axle housing. A steer knuckle is connected to an end portion of the axle housing by king pins. The steer knuckle rotates relative to the axle housing about the king pins. A wheel end assembly including a brake drum and a pair of brake shoes is supported on an outer wall of the steer knuckle. Preferably, one end of a cam shaft is supported by the wheel end assembly, such as by a spindle. According to the present invention, the steer knuckle includes a boss extending from a portion of the steer knuckle. The boss includes a hole, and preferably, a bushing is received in the hole to support the other end of the cam shaft. Other brake components such as an air chamber, rod, and a brake adjuster are supported by the knuckle and connected to the cam shaft to rotate the cam shaft about its axis and force the brake shoes away from one another with a cam and into engagement with the brake drum.

    Cavity down HBGA package structure
    38.
    发明授权
    Cavity down HBGA package structure 失效
    腔下HBGA封装结构

    公开(公告)号:US5910686A

    公开(公告)日:1999-06-08

    申请号:US121792

    申请日:1998-07-23

    摘要: An integrated-circuit die is attached to the top interior surface of a die-cavity formed in the underside of a heat spreader. The other side of the integrated circuit die has a number of wire-bonding pads formed thereupon. A plurality of bonding-wire loops at least some of which are completely contained within the die-cavity to allow the part of the encapsulation or lid to be as thin as possible, while still covering the bonding wires. A first portion of a insulated tape layer covers the lower outside surface of the die-carrier/heat spreader and another portion of the insulated tape layer extends inside of the die-cavity and has a number of wire-bonding sites formed thereupon. A plurality of bonding-wire loops are bonded to one of the wire-bonding pads formed on the integrated-circuit die and the wire-bonding sites formed on the insulated tape layer. Conductive traces connect the wire-bonding sites located inside of the die-cavity to respective selective solderable areas arranged in a grid pattern for receipt of solder balls. Encapsulation material or a ceramic or metal lid cover and seal the integrated-circuit die and the bonding wires in the die-cavity. The wire-bonding sites formed in the die-cavity are adhesively fixed to the top interior surface of the die-cavity. To increase bonding-wire density, the wire-bonding sites and the wire-bonding pads on the integrated-circuit die are arranged in two or more rows. Other wire-bonding sites are optionally formed outside of the die-cavity.

    摘要翻译: 集成电路模具附接到形成在散热器下侧的模腔的顶部内表面。 集成电路管芯的另一侧具有在其上形成的多个引线接合焊盘。 多个接合线环中的至少一些被完全包含在模腔内,以允许封装或盖的一部分尽可能薄,同时仍然覆盖接合线。 绝缘胶带层的第一部分覆盖模具载体/散热器的下外表面,并且绝缘带层的另一部分在模腔内部延伸并且在其上形成多个引线接合部位。 多个接合线环接合到形成在集成电路管芯上的引线接合焊盘之一和形成在绝缘带层上的引线接合位置。 导电迹线将位于模腔内的引线接合位置连接到以栅格图案布置的相应的可选择可焊接区域以接收焊球。 封装材料或陶瓷或金属盖盖,并密封集成电路管芯和模腔中的接合线。 形成在模腔中的引线接合位置被粘合地固定到模腔的顶部内表面。 为了增加接合线密度,集成电路晶片上的引线接合位置和引线接合焊盘被布置成两行或更多行。 可选地,在模腔的外部形成其它引线接合位置。

    Dual transparent latch
    40.
    发明授权
    Dual transparent latch 失效
    双透明闩锁

    公开(公告)号:US5424996A

    公开(公告)日:1995-06-13

    申请号:US953158

    申请日:1992-09-29

    摘要: A dual transparent latch circuit is disclosed comprising two latches cross coupled together by two control lines to enable the latches collectively to input and output data at twice the frequency of the master clock frequency which controls the timing of each latch individually. The control lines are controlled by a clock generator such that one latch is enabled to receive and store data while the other latch is enabled to output data stored therein. At the same time, the latch receiving and storing the data is disabled from providing an output of the stored data and the latch providing the output is disabled from receiving and storing the data. The clock generator switches the states of the control lines such that they enable or disable the input of data to and output of data from the latches on each phase of the master clock signal. A dual transparent latch with triple edge timing is also disclosed. A method for generating a master signal having a master frequency and selectively enabling inputs at an input data rate greater than the master frequency to input data into memory and selectively enabling outputs at the input data rate to output data from memory.

    摘要翻译: 公开了一种双透明锁存电路,其包括由两个控制线交叉耦合在一起的两个锁存器,以使得锁存器能够共同地以主控制器频率的频率的两倍输入和输出,该时钟频率分别控制每个锁存器的定时。 控制线由时钟发生器控制,使得一个锁存器能够接收和存储数据,而另一个锁存器被使能以输出存储在其中的数据。 同时,禁止接收和存储数据的锁存器提供存储的数据的输出,并且提供输出的锁存器被禁止接收和存储数据。 时钟发生器切换控制线的状态,使得它们能够或禁止从主时钟信号的每个相位上的锁存器输入数据并输出数据。 还公开了具有三重边沿定时的双透明锁存器。 一种用于产生具有主频率的主信号并且以大于主频率的输入数据速率选择性地启用输入的方法,用于将数据输入到存储器中,并且以输入数据速率有选择地使得输出能够从存储器输出数据。