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44 条记录 (耗时 0.034 秒)

    SYSTEMS AND METHODS FOR POWER TRANSFER BASED ON RESONANCE COUPLING OF INDUCTORS
    32.
    发明申请
    SYSTEMS AND METHODS FOR POWER TRANSFER BASED ON RESONANCE COUPLING OF INDUCTORS 有权
    基于电感耦合的功率传递系统与方法

    公开(公告)号：US20120326773A1

    公开(公告)日：2012-12-27

    申请号：US13169364

    申请日：2011-06-27

    申请人： Baris Posat ,  Roberto Alini

    发明人： Baris Posat ,  Roberto Alini

    IPC分类号： H03K5/00

    CPC分类号： H01F38/14 ,  H01F2019/085 ,  H01L23/495 ,  H01L23/5227 ,  H01L23/645 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2924/30107 ,  H02J5/005 ,  H02J50/12 ,  H02J50/80 ,  H01L2924/00

    摘要： An integrated circuit (IC) includes first and second resonator circuits and an isolation barrier. The first resonator circuit includes first and second inductors, wherein the first resonator circuit is connected to a supply voltage. The second resonator circuit includes third and fourth inductors, wherein the second resonator circuit is matched to the first resonator circuit. The isolation barrier separates the first and second resonator circuits. The first and second inductors are inductively coupled to the third and fourth inductors, respectively, thereby providing for transfer of power from the first resonator circuit across the isolation barrier to the second resonator circuit.

    摘要翻译： 集成电路（IC）包括第一和第二谐振器电路和隔离屏障。 第一谐振器电路包括第一和第二电感器，其中第一谐振器电路连接到电源电压。 第二谐振器电路包括第三和第四电感器，其中第二谐振器电路与第一谐振器电路匹配。 隔离栅分离第一和第二谐振器电路。 第一和第二电感器分别电感耦合到第三和第四电感器，从而提供从第一谐振器电路跨越隔离屏障到第二谐振器电路的功率传递。

    Write driver with power optimization and interconnect impedance matching
    33.
    发明授权
    Write driver with power optimization and interconnect impedance matching 有权
    写入驱动器，具有电源优化和互连阻抗匹配

    公开(公告)号：US07375909B2

    公开(公告)日：2008-05-20

    申请号：US10824096

    申请日：2004-04-14

    申请人： Alessandro Venca ,  Roberto Alini ,  Baris Posat

    发明人： Alessandro Venca ,  Roberto Alini ,  Baris Posat

    IPC分类号： G11B5/09

    CPC分类号： G11B5/02

    摘要： A write driver for driving a write current through a write head connected to the write head by an interconnect or flexible transmission line. The write driver includes a circuit matching an output impedance of the write driver to the odd characteristic impedance of the interconnect and includes a current source generating a current output to the write head. The write driver provides a current amplification effect as the output current is half the write current driven through the write coil. The impedance matching circuit includes an output resistor with a resistance equal to the odd characteristic impedance of the interconnect. The write driver includes a voltage source that operates to maintain a voltage drop of zero on the output resistor during the initial period of twice the transmission delay of the interconnect.

    摘要翻译： 用于通过互连或柔性传输线连接到写入头的写入头来驱动写入电流的写入驱动器。 写驱动器包括将写驱动器的输出阻抗与互连的奇特特性阻抗匹配的电路，并且包括产生到写头的电流输出的电流源。 写入驱动器提供电流放大效应，因为输出电流是通过写入线圈驱动的写入电流的一半。 阻抗匹配电路包括具有等于互连的奇特性阻抗的电阻的输出电阻器。 写入驱动器包括电压源，其操作以在互连的传输延迟的两倍的初始周期期间在输出电阻器上保持零电压降。

    Write driver with improved boosting circuit and interconnect impedance matching
    34.
    发明授权
    Write driver with improved boosting circuit and interconnect impedance matching 有权
    写驱动器具有改进的升压电路和互连阻抗匹配

    公开(公告)号：US07365928B2

    公开(公告)日：2008-04-29

    申请号：US11105174

    申请日：2005-04-13

    申请人： Alessandro Venca ,  Roberto Alini ,  Baris Posat

    发明人： Alessandro Venca ,  Roberto Alini ,  Baris Posat

    IPC分类号： G11B5/02

    CPC分类号： G11B5/02 ,  G11B5/022 ,  G11B2005/0018 ,  H02M3/07

    摘要： A write driver driving a write current through a head connected to the write head by an interconnect. The write driver includes a circuit matching output resistance to the odd characteristic impedance of the interconnect and a voltage boosting circuit. The voltage boosting circuit in connected between a high voltage reference or supply voltage and a low voltage reference, and includes a pair of current sources, such as MOS transistors, connected to the input node of a single capacitor. During the overshoot duration, the current sources selectively operate at saturation to generate a pulsed current with an amplitude of half the load current. The recharge of the capacitor is done with the load current.

    摘要翻译： 一个写入驱动器通过一个连接到写入头的头驱动写入电流。 写驱动器包括匹配输出电阻到互连的奇特特性阻抗的电路和升压电路。 连接在高电压基准或电源电压和低电压基准之间的升压电路，并且包括连接到单个电容器的输入节点的一对电流源，例如MOS晶体管。 在过冲持续时间期间，电流源选择性地工作在饱和状态以产生具有一半负载电流幅度的脉冲电流。 电容器的充电由负载电流完成。

    One-time programmable circuit exploiting BJT hFE degradation
    36.
    发明申请
    One-time programmable circuit exploiting BJT hFE degradation 有权
    一次性可编程电路利用BJT hFE降解

    公开(公告)号：US20060262590A1

    公开(公告)日：2006-11-23

    申请号：US11115538

    申请日：2005-04-27

    申请人： Roberto Alini ,  Sergio Rovati ,  Eric Vandenbossche ,  Christopher Paskins

    发明人： Roberto Alini ,  Sergio Rovati ,  Eric Vandenbossche ,  Christopher Paskins

    IPC分类号： G11C17/00

    CPC分类号： G11C17/16

    摘要： A one-time programmable circuit uses forced BJT hFE degradation to permanently store digital information as a logic zero or logic one state. The forced degradation is accomplished by applying a voltage or current to the BJT for a specific time to the reversed biased base-emitter junction, allowing a significant degradation of the junction without destroying it.

    摘要翻译： 一次性可编程电路使用强制BJT低电平劣化将数字信息永久存储为逻辑0或逻辑1状态。 强制退化是通过向BJT施加一个特定时间的电压或电流到反向偏置的基极 - 发射极接点来实现的，从而允许接合处的显着劣化而不破坏它。

    Write head driver circuit and method for writing to a memory disk
    37.
    发明授权
    Write head driver circuit and method for writing to a memory disk 有权
    写头驱动电路和写入存储盘的方法

    公开(公告)号：US06970316B2

    公开(公告)日：2005-11-29

    申请号：US09991557

    申请日：2001-11-09

    申请人： Alessandro Venca ,  Baris Posat ,  Kemal Ozanoglu ,  Roberto Alini

    发明人： Alessandro Venca ,  Baris Posat ,  Kemal Ozanoglu ,  Roberto Alini

    IPC分类号： G11B5/09 ,  G11B5/00 ,  G11B5/012 ,  G11B5/02 ,  G11B15/12

    CPC分类号： G11B5/022 ,  G11B5/012 ,  G11B5/02 ,  G11B5/09 ,  G11B2005/0013

    摘要： A circuit and method are disclosed for relatively rapidly causing the current flowing through a write head to transition between steady states without generating an appreciable amount of capacitively-coupled noise. Embodiments of the present invention generally provide drive voltage signals to the write head that have no common mode voltage levels during transitions between steady state current levels in the write head. In other words, the drive voltage signals applied to the write head are substantially entirely differential during write head current transitions. In an exemplary embodiment of the present invention, a driver circuit includes switching circuitry connected between the terminals of the write head and reference voltage supplies, such as positive and negative voltage supplies. The driver circuit further includes timing circuitry that generates control signals for controlling the switching circuitry.

    摘要翻译： 公开了一种电路和方法，用于相对快速地使流过写入头的电流在稳态之间转变而不产生可观量的电容耦合噪声。 本发明的实施例通常向写入头提供在写入头中的稳态电流电平之间的转换期间不具有共模电压电平的驱动电压信号。 换句话说，施加到写入头的驱动电压信号在写入头电流转换期间基本上完全不同。 在本发明的示例性实施例中，驱动器电路包括连接在写入头的端子和参考电压源（例如正和负电压源）之间的开关电路。 驱动器电路还包括产生用于控制开关电路的控制信号的定时电路。

    Voltage regulator operable over a wide range of supply voltage
    38.
    发明授权
    Voltage regulator operable over a wide range of supply voltage 有权
    电压调节器可在宽范围的电源电压下工作

    公开(公告)号：US06963460B2

    公开(公告)日：2005-11-08

    申请号：US10295263

    申请日：2002-11-14

    申请人： Manish Jain ,  Roberto Alini

    发明人： Manish Jain ,  Roberto Alini

    IPC分类号： G11B20/10 ,  G05F1/10 ,  G11B5/02 ,  G11B5/09 ,  G11B19/00

    CPC分类号： G11B19/00 ,  G11B19/2063

    摘要： A voltage regulator includes an output node and first and second regulator circuits. The first regulator circuit generates a first regulated voltage on the output node when a supply voltage equals or exceeds a predetermined threshold, and the second regulator circuit generates a second regulated voltage on the output node when the supply voltage is less than the predetermined threshold.

    摘要翻译： 电压调节器包括输出节点和第一和第二调节器电路。 当电源电压等于或超过预定阈值时，第一调节器电路在输出节点上产生第一调节电压，并且当电源电压小于预定阈值时，第二调节器电路在输出节点上产生第二调节电压。

    Write driver with improved boosting circuit and interconnect impedance matching
    39.
    发明申请
    Write driver with improved boosting circuit and interconnect impedance matching 有权
    写驱动器具有改进的升压电路和互连阻抗匹配

    公开(公告)号：US20050237785A1

    公开(公告)日：2005-10-27

    申请号：US11105174

    申请日：2005-04-13

    申请人： Alessandro Venca ,  Roberto Alini ,  Baris Posat

    发明人： Alessandro Venca ,  Roberto Alini ,  Baris Posat

    IPC分类号： G05F3/26 ,  G11B5/00 ,  G11B5/02 ,  G11B5/09 ,  H02M3/07 ,  G11C11/00

    CPC分类号： G11B5/02 ,  G11B5/022 ,  G11B2005/0018 ,  H02M3/07

    摘要： A write driver driving a write current through a head connected to the write head by an interconnect. The write driver includes a circuit matching output resistance to the odd characteristic impedance of the interconnect and a voltage boosting circuit. The voltage boosting circuit in connected between a high voltage reference or supply voltage and a low voltage reference, and includes a pair of current sources, such as MOS transistors, connected to the input node of a single capacitor. During the overshoot duration, the current sources selectively operate at saturation to generate a pulsed current with an amplitude of half the load current. The recharge of the capacitor is done with the load current.

    摘要翻译： 一个写入驱动器通过一个连接到写入头的头驱动写入电流。 写驱动器包括匹配输出电阻到互连的奇特特性阻抗的电路和升压电路。 连接在高电压基准或电源电压和低电压基准之间的升压电路，并且包括连接到单个电容器的输入节点的一对电流源，例如MOS晶体管。 在过冲持续时间期间，电流源选择性地工作在饱和状态以产生具有一半负载电流幅度的脉冲电流。 电容器的充电由负载电流完成。