公开(公告)号：US07035028B2

公开(公告)日：2006-04-25

申请号：US10843823

申请日：2004-05-12

Applicant: Alessandro Venca ,  Roberto Alini ,  Baris Posat

Inventor： Alessandro Venca ,  Roberto Alini ,  Baris Posat

IPC: G11B5/09

CPC classification number: G11B5/09 ,  G11B2005/0016 ,  H02M3/073

Abstract: A write driver driving a write current through a head connected to the write head by an interconnect. The write driver includes a circuit matching output resistance to the odd characteristic impedance of the interconnect and a voltage boosting circuit. The voltage boosting circuit in connected between a high voltage reference or supply voltage and a low voltage reference, and includes a current source, such as a MOS transistor, connected to the input node of a capacitor. During the overshoot duration, the current source operates at saturation to generate a pulsed current with an amplitude of half the load current. The circuit includes another transistor in series with the current generator between the capacitor and the driver output. A forward bias diode is connected between the capacitor output node and high voltage reference and enters reverse bias during overshoot duration swinging the driver output voltage above supply voltage.

Abstract translation: 一个写入驱动器通过一个连接到写入头的头驱动写入电流。 写驱动器包括匹配输出电阻到互连的奇特特性阻抗的电路和升压电路。 连接在高电压基准或电源电压和低电压基准之间的升压电路，并且包括连接到电容器的输入节点的诸如MOS晶体管的电流源。 在过冲持续时间期间，电流源工作在饱和状态以产生具有一半负载电流幅度的脉冲电流。 电路包括与电容器和驱动器输出之间的电流发生器串联的另一个晶体管。 正向偏置二极管连接在电容器输出节点和高电压基准之间，并在驱动器输出电压高于电源电压的过冲持续时间期间进入反向偏置。

公开(公告)号：US08625242B2

公开(公告)日：2014-01-07

申请号：US13197136

申请日：2011-08-03

Applicant: Roberto Alini ,  Rajesh Kumar Gupta ,  Baris Posat

Inventor： Roberto Alini ,  Rajesh Kumar Gupta ,  Baris Posat

IPC: H02H3/20

CPC classification number: H04L25/0266 ,  H01F27/40 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48228 ,  H01L2924/00014 ,  H01L2224/45099

Abstract: A system includes a transmitter, a receiver, a isolation barrier, and a fuse. The isolation barrier is connected to the transmitter. The fuse is connected between the isolation barrier and the receiver. The isolation barrier prevents current flow from the transmitter to the receiver when a voltage across the isolation barrier is less than a first breakdown voltage. The isolation barrier short circuits when the voltage across the isolation barrier is greater than or equal to the first breakdown voltage. The fuse opens when the isolation barrier short circuits. When open, the fuse has a second breakdown voltage that is greater than the first breakdown voltage.

Abstract translation: 系统包括发射机，接收机，隔离屏障和保险丝。 隔离屏障连接到变送器。 保险丝连接在隔离屏障和接收器之间。 当隔离隔离层上的电压小于第一击穿电压时，隔离屏障防止电流从发射器流向接收器。 当隔离屏障上的电压大于或等于第一击穿电压时，隔离栅短路。 保险丝断开时隔离屏障短路。 当断开时，保险丝的第二击穿电压大于第一击穿电压。

公开(公告)号：US20130033791A1

公开(公告)日：2013-02-07

申请号：US13197136

申请日：2011-08-03

Applicant: Roberto Alini ,  Rajesh Kumar Gupta ,  Baris Posat

Inventor： Roberto Alini ,  Rajesh Kumar Gupta ,  Baris Posat

IPC: H02H3/20 ,  H02H3/24

CPC classification number: H04L25/0266 ,  H01F27/40 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48228 ,  H01L2924/00014 ,  H01L2224/45099

Abstract: A system includes a transmitter, a receiver, a isolation barrier, and a fuse. The isolation barrier is connected to the transmitter. The fuse is connected between the isolation barrier and the receiver. The isolation barrier prevents current flow from the transmitter to the receiver when a voltage across the isolation barrier is less than a first breakdown voltage. The isolation barrier short circuits when the voltage across the isolation barrier is greater than or equal to the first breakdown voltage. The fuse opens when the isolation barrier short circuits. When open, the fuse has a second breakdown voltage that is greater than the first breakdown voltage.

Abstract translation: 系统包括发射机，接收机，隔离屏障和保险丝。 隔离屏障连接到变送器。 保险丝连接在隔离屏障和接收器之间。 当隔离隔离层上的电压小于第一击穿电压时，隔离屏障防止电流从发射器流向接收器。 当隔离屏障上的电压大于或等于第一击穿电压时，隔离栅短路。 保险丝断开时隔离屏障短路。 当断开时，保险丝的第二击穿电压大于第一击穿电压。

公开(公告)号：US20050254159A1

公开(公告)日：2005-11-17

申请号：US10843823

申请日：2004-05-12

Applicant: Alessandro Venca ,  Roberto Alini ,  Baris Posat

Inventor： Alessandro Venca ,  Roberto Alini ,  Baris Posat

IPC: G11B5/09 ,  G05F3/26 ,  G11B5/00 ,  G11B5/02 ,  H02M3/07

CPC classification number: G11B5/09 ,  G11B2005/0016 ,  H02M3/073

Abstract: A write driver driving a write current through a head connected to the write head by an interconnect. The write driver includes a circuit matching output resistance to the odd characteristic impedance of the interconnect and a voltage boosting circuit. The voltage boosting circuit in connected between a high voltage reference or supply voltage and a low voltage reference, and includes a current source, such as a MOS transistor, connected to the input node of a capacitor. During the overshoot duration, the current source operates at saturation to generate a pulsed current with an amplitude of half the load current. The circuit includes another transistor in series with the current generator between the capacitor and the driver output. A forward bias diode is connected between the capacitor output node and high voltage reference and enters reverse bias during overshoot duration swinging the driver output voltage above supply voltage.

Abstract translation: 一个写入驱动器通过一个连接到写入头的头驱动写入电流。 写驱动器包括匹配输出电阻到互连的奇特特性阻抗的电路和升压电路。 连接在高电压基准或电源电压和低电压基准之间的升压电路，并且包括连接到电容器的输入节点的诸如MOS晶体管的电流源。 在过冲持续时间期间，电流源工作在饱和状态以产生具有一半负载电流幅度的脉冲电流。 电路包括与电容器和驱动器输出之间的电流发生器串联的另一个晶体管。 正向偏置二极管连接在电容器输出节点和高电压基准之间，并在驱动器输出电压高于电源电压的过冲持续时间期间进入反向偏置。

公开(公告)号：US20050231843A1

公开(公告)日：2005-10-20

申请号：US10824096

申请日：2004-04-14

Applicant: Alessandro Venca ,  Roberto Alini ,  Baris Posat

Inventor： Alessandro Venca ,  Roberto Alini ,  Baris Posat

IPC: G11B5/09 ,  G05F3/26 ,  G11B5/02 ,  H04L25/02

CPC classification number: G11B5/02

Abstract: A write driver for driving a write current through a write head connected to the write head by an interconnect or flexible transmission line. The write driver includes a circuit matching an output impedance of the write driver to the odd characteristic impedance of the interconnect and includes a current source generating a current output to the write head. The write driver provides a current amplification effect as the output current is half the write current driven through the write coil. The impedance matching circuit includes an output resistor with a resistance equal to the odd characteristic impedance of the interconnect. The write driver includes a voltage source that operates to maintain a voltage drop of zero on the output resistor during the initial period of twice the transmission delay of the interconnect.

Abstract translation: 用于通过互连或柔性传输线连接到写入头的写入头来驱动写入电流的写入驱动器。 写驱动器包括将写驱动器的输出阻抗与互连的奇特特性阻抗匹配的电路，并且包括产生到写头的电流输出的电流源。 写入驱动器提供电流放大效应，因为输出电流是通过写入线圈驱动的写入电流的一半。 阻抗匹配电路包括具有等于互连的奇特性阻抗的电阻的输出电阻器。 写入驱动器包括电压源，其操作以在互连的传输延迟的两倍的初始周期期间在输出电阻器上保持零电压降。

公开(公告)号：US08890368B2

公开(公告)日：2014-11-18

申请号：US13169364

申请日：2011-06-27

Applicant: Baris Posat ,  Roberto Alini

Inventor： Baris Posat ,  Roberto Alini

IPC: H01F27/42 ,  H01F37/00 ,  H01F38/00 ,  H02M3/335 ,  H02J5/00 ,  H01L23/522 ,  H01L23/64 ,  H01L23/495 ,  H01F19/08

CPC classification number: H01F38/14 ,  H01F2019/085 ,  H01L23/495 ,  H01L23/5227 ,  H01L23/645 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2924/30107 ,  H02J5/005 ,  H02J50/12 ,  H02J50/80 ,  H01L2924/00

Abstract: An integrated circuit (IC) includes first and second resonator circuits and an isolation barrier. The first resonator circuit includes first and second inductors, wherein the first resonator circuit is connected to a supply voltage. The second resonator circuit includes third and fourth inductors, wherein the second resonator circuit is matched to the first resonator circuit. The isolation barrier separates the first and second resonator circuits. The first and second inductors are inductively coupled to the third and fourth inductors, respectively, thereby providing for transfer of power from the first resonator circuit across the isolation barrier to the second resonator circuit.

Abstract translation: 集成电路（IC）包括第一和第二谐振器电路和隔离屏障。 第一谐振器电路包括第一和第二电感器，其中第一谐振器电路连接到电源电压。 第二谐振器电路包括第三和第四电感器，其中第二谐振器电路与第一谐振器电路匹配。 隔离栅分离第一和第二谐振器电路。 第一和第二电感器分别感应耦合到第三和第四电感器，从而提供从第一谐振器电路跨越隔离屏障到第二谐振器电路的功率传递。

公开(公告)号：US20120326773A1

公开(公告)日：2012-12-27

申请号：US13169364

申请日：2011-06-27

Applicant: Baris Posat ,  Roberto Alini

Inventor： Baris Posat ,  Roberto Alini

IPC: H03K5/00

CPC classification number: H01F38/14 ,  H01F2019/085 ,  H01L23/495 ,  H01L23/5227 ,  H01L23/645 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2924/30107 ,  H02J5/005 ,  H02J50/12 ,  H02J50/80 ,  H01L2924/00

Abstract: An integrated circuit (IC) includes first and second resonator circuits and an isolation barrier. The first resonator circuit includes first and second inductors, wherein the first resonator circuit is connected to a supply voltage. The second resonator circuit includes third and fourth inductors, wherein the second resonator circuit is matched to the first resonator circuit. The isolation barrier separates the first and second resonator circuits. The first and second inductors are inductively coupled to the third and fourth inductors, respectively, thereby providing for transfer of power from the first resonator circuit across the isolation barrier to the second resonator circuit.

Abstract translation: 集成电路（IC）包括第一和第二谐振器电路和隔离屏障。 第一谐振器电路包括第一和第二电感器，其中第一谐振器电路连接到电源电压。 第二谐振器电路包括第三和第四电感器，其中第二谐振器电路与第一谐振器电路匹配。 隔离栅分离第一和第二谐振器电路。 第一和第二电感器分别电感耦合到第三和第四电感器，从而提供从第一谐振器电路跨越隔离屏障到第二谐振器电路的功率传递。

公开(公告)号：US07375909B2

公开(公告)日：2008-05-20

申请号：US10824096

申请日：2004-04-14

Applicant: Alessandro Venca ,  Roberto Alini ,  Baris Posat

Inventor： Alessandro Venca ,  Roberto Alini ,  Baris Posat

IPC: G11B5/09

CPC classification number: G11B5/02

Abstract: A write driver for driving a write current through a write head connected to the write head by an interconnect or flexible transmission line. The write driver includes a circuit matching an output impedance of the write driver to the odd characteristic impedance of the interconnect and includes a current source generating a current output to the write head. The write driver provides a current amplification effect as the output current is half the write current driven through the write coil. The impedance matching circuit includes an output resistor with a resistance equal to the odd characteristic impedance of the interconnect. The write driver includes a voltage source that operates to maintain a voltage drop of zero on the output resistor during the initial period of twice the transmission delay of the interconnect.

Abstract translation: 用于通过互连或柔性传输线连接到写入头的写入头来驱动写入电流的写入驱动器。 写驱动器包括将写驱动器的输出阻抗与互连的奇特特性阻抗匹配的电路，并且包括产生到写头的电流输出的电流源。 写入驱动器提供电流放大效应，因为输出电流是通过写入线圈驱动的写入电流的一半。 阻抗匹配电路包括具有等于互连的奇特性阻抗的电阻的输出电阻器。 写入驱动器包括电压源，其操作以在互连的传输延迟的两倍的初始周期期间在输出电阻器上保持零电压降。

公开(公告)号：US07365928B2

公开(公告)日：2008-04-29

申请号：US11105174

申请日：2005-04-13

Applicant: Alessandro Venca ,  Roberto Alini ,  Baris Posat

Inventor： Alessandro Venca ,  Roberto Alini ,  Baris Posat

IPC: G11B5/02

CPC classification number: G11B5/02 ,  G11B5/022 ,  G11B2005/0018 ,  H02M3/07

Abstract: A write driver driving a write current through a head connected to the write head by an interconnect. The write driver includes a circuit matching output resistance to the odd characteristic impedance of the interconnect and a voltage boosting circuit. The voltage boosting circuit in connected between a high voltage reference or supply voltage and a low voltage reference, and includes a pair of current sources, such as MOS transistors, connected to the input node of a single capacitor. During the overshoot duration, the current sources selectively operate at saturation to generate a pulsed current with an amplitude of half the load current. The recharge of the capacitor is done with the load current.

Abstract translation: 一个写入驱动器通过一个连接到写入头的头驱动写入电流。 写驱动器包括匹配输出电阻到互连的奇特特性阻抗的电路和升压电路。 连接在高电压基准或电源电压和低电压基准之间的升压电路，并且包括连接到单个电容器的输入节点的一对电流源，例如MOS晶体管。 在过冲持续时间期间，电流源选择性地工作在饱和状态以产生具有一半负载电流幅度的脉冲电流。 电容器的充电由负载电流完成。

公开(公告)号：US06970316B2

公开(公告)日：2005-11-29

申请号：US09991557

申请日：2001-11-09

Applicant: Alessandro Venca ,  Baris Posat ,  Kemal Ozanoglu ,  Roberto Alini

Inventor： Alessandro Venca ,  Baris Posat ,  Kemal Ozanoglu ,  Roberto Alini

IPC: G11B5/09 ,  G11B5/00 ,  G11B5/012 ,  G11B5/02 ,  G11B15/12

CPC classification number: G11B5/022 ,  G11B5/012 ,  G11B5/02 ,  G11B5/09 ,  G11B2005/0013

Abstract: A circuit and method are disclosed for relatively rapidly causing the current flowing through a write head to transition between steady states without generating an appreciable amount of capacitively-coupled noise. Embodiments of the present invention generally provide drive voltage signals to the write head that have no common mode voltage levels during transitions between steady state current levels in the write head. In other words, the drive voltage signals applied to the write head are substantially entirely differential during write head current transitions. In an exemplary embodiment of the present invention, a driver circuit includes switching circuitry connected between the terminals of the write head and reference voltage supplies, such as positive and negative voltage supplies. The driver circuit further includes timing circuitry that generates control signals for controlling the switching circuitry.

Abstract translation: 公开了一种电路和方法，用于相对快速地使流过写入头的电流在稳态之间转变而不产生可观量的电容耦合噪声。 本发明的实施例通常向写入头提供在写入头中的稳态电流电平之间的转换期间不具有共模电压电平的驱动电压信号。 换句话说，施加到写入头的驱动电压信号在写入头电流转换期间基本上完全不同。 在本发明的示例性实施例中，驱动器电路包括连接在写入头的端子和参考电压源（例如正和负电压源）之间的开关电路。 驱动器电路还包括产生用于控制开关电路的控制信号的定时电路。