公开(公告)号：US20210391012A1

公开(公告)日：2021-12-16

申请号：US16899860

申请日：2020-06-12

Applicant: SanDisk Technologies LLC

Inventor： Muhammad Masuduzzaman ,  Deepanshu Dutta

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/24 ,  G11C16/34 ,  G11C16/14 ,  G11C16/26

Abstract: A storage device may be configured to determine data states for a first set of memory cells, of an array of memory cells, that are part of a logical N−1 neighboring word line that is adjacent to a selected word line. The storage device may be further configured to determine a program voltage configuration based on the data states. The storage device may be further configured to determine, using the program voltage configuration, a program operation on the selected word line to iteratively program respective memory cells, of a second set of memory cells that are part of the selected word line. Determining the data states, determining the program voltage configuration, and performing the program operation may be repeated until a program stop condition is satisfied.

公开(公告)号：US20210134372A1

公开(公告)日：2021-05-06

申请号：US16676023

申请日：2019-11-06

Applicant: SanDisk Technologies LLC

Inventor： Zhiping Zhang ,  Muhammad Masuduzzaman ,  Huai-Yuan Tseng ,  Peng Zhang ,  Dengtao Zhao ,  Deepanshu Dutta

IPC: G11C16/26 ,  G11C16/10 ,  G11C16/34 ,  G06F3/06

Abstract: A method reading memory using bi-directional sensing, including programming first memory cells coupled to a first word-line using a normal programming order; programming second memory cells coupled to a second word-line using a normal programming order; reading data from the first memory cells by applying a normal sensing operation to the first word-line; and reading data from the second memory cells by applying a reverse sensing operation to the second word-line. Methods also include receiving an error associated with reading data from the first memory cells; and then reading the data from the first memory cells by applying a reverse sensing operation to the first word-line. Method also include receiving an error associated with reading the data from the second memory cells; and then reading the data from the second memory cells by applying a normal sensing operation to the second word-line.

公开(公告)号：US20210134370A1

公开(公告)日：2021-05-06

申请号：US16701450

申请日：2019-12-03

Applicant: SanDisk Technologies LLC

Inventor： Zhiping Zhang ,  Muhammad Masuduzzaman ,  Huai-Yuan Tseng ,  Dengtao Zhao ,  Deepanshu Dutta

IPC: G11C16/12 ,  G11C16/10 ,  G11C16/24 ,  G11C16/34 ,  G11C16/26

Abstract: A method of concurrently programming a memory. Various methods include: applying a non-negative voltage on a first bit line coupled to a first memory cell; applying a negative voltage on a second bit line coupled to a second memory cell, where the negative voltage is generated using triple-well technology; then applying a programming pulse to the first and second memory cells concurrently; and in response, programming the first and second memory cells to different states. The methods also include applying a quick pass write operation to the first and second memory cells, by: applying a quick pass write voltage to the first bit line coupled to the first memory cell, where the quick pass write voltage is higher than the non-negative voltage; applying a negative quick pass write voltage to the second bit line coupled to the first memory cell, where the negative quick pass write voltage is generated using triple-well technology.

公开(公告)号：US09842657B1

公开(公告)日：2017-12-12

申请号：US15599243

申请日：2017-05-18

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Deepanshu Dutta ,  Xiaochang Miao ,  Muhammad Masuduzzaman

IPC: G11C16/06 ,  G11C16/34 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  G11C16/24

CPC classification number: G11C16/3459 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  G11C16/32 ,  G11C16/3481 ,  G11C2211/5622

Abstract: Multi-state programming of non-volatile memory cells, where cells being programmed to different target states are programmed concurrently, is performed by modulating the program speed of each state using a controlled amount of state-dependent weak boosting in their respective channels. In one example, the channel boosting is controlled by using a multi-stair word line ramp in conjunction with raising of the voltage on bit lines at a time based on the corresponding memory cell's target state.