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公开(公告)号：US12205657B2
公开(公告)日：2025-01-21
申请号：US17895412
申请日：2022-08-25
Applicant: SanDisk Technologies LLC
Inventor： Xiang Yang , Henry Chin , Erika Penzo , Muhammad Masuduzzaman
Abstract: Technology is disclosed herein for smart verify in a memory system that has a four bit per cell program mode (or X4 mode) and also a three bit per cell program mode (or X3 mode). The X3 mode uses a three-bit gray code that is based on a four-bit gray code of the X4 mode. The memory system skips verify of states in the X3 mode, while using a considerable portion of the programming logic from the X4 mode. In one X3 mode the memory system skips B-state verify while the number of memory cells having a Vt above an A-state verify voltage is below a threshold. In one X3 mode the memory system determines whether to skip verify for a first set of data states based on a first test and determines whether to skip verify for a second set of data states based on a second test.
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公开(公告)号：US12079496B2
公开(公告)日：2024-09-03
申请号：US17901310
申请日：2022-09-01
Applicant: SanDisk Technologies LLC
Inventor： Chin-Yi Chen , Muhammad Masuduzzaman , Xiang Yang
IPC: G06F3/06
CPC classification number: G06F3/0632 , G06F3/0604 , G06F3/0679
Abstract: Technology is disclosed herein for managing timing parameters when programming memory cells. Timing parameters used sub-clocks in an MLC program mode may also be used for those same sub-clocks in a first SLC program mode. However, in a second SLC program mode a different set of timing parameters may be used for that set of sub-clocks. Using the same set of timing parameters for the MLC program mode and the first SLC program mode saves storage space. However, the timing parameters for the MLC program mode may be slower than desired for SLC programming. A different set of timing parameters may be used for the second SLC program mode to provide for faster program operation. Moreover, the different set of timing parameters used for the faster SLC program mode do not require storage of a separate set of timing parameters.
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公开(公告)号：US20230386569A1
公开(公告)日：2023-11-30
申请号：US17825193
申请日：2022-05-26
Applicant: SanDisk Technologies LLC
Inventor： Xiang Yang , Muhammad Masuduzzaman , Jiacen Guo
CPC classification number: G11C11/5628 , G11C11/5671 , G11C16/0483 , G11C16/10
Abstract: A method for programming a memory array of a non-volatile memory structure, the memory comprising a population of MLC NAND-type memory cells, wherein the method comprises applying: (1) an inhibit condition to one or more bit lines of the memory array, and (2) a zero voltage condition to one or more bit lines of the memory array such that less than half of the adjacent bit lines of the memory array experience a voltage swing between the inhibit condition and the zero voltage condition.
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公开(公告)号：US11475967B1
公开(公告)日：2022-10-18
申请号：US17307626
申请日：2021-05-04
Applicant: SanDisk Technologies LLC
Inventor： Xue Pitner , Muhammad Masuduzzaman , Ravi Kumar
IPC: G11C16/10 , G11C16/34 , G11C16/04 , G11C16/26 , G11C16/08 , H01L27/11565 , G11C11/56 , H01L27/11556 , H01L27/11582 , H01L27/11519
Abstract: The non-volatile memory includes a control circuitry that is communicatively coupled to an array of memory cells that are arranged word lines. The control circuitry is configured to program the memory cells using a multi-pass programming operation which includes a first pass and a second pass. The first pass programs the memory cells to a first number of data states, and the second pass programs the memory cells to a greater second number of data states. For at least one word line, during the second pass, a voltage that is applied to at least one memory cell is reduced from a verify voltage by an offset which is determined as a function of a data state of an adjacent memory cell of an adjacent word line and wherein the first pass but not the second pass has been completed in the adjacent word line.
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公开(公告)号：US11423993B2
公开(公告)日：2022-08-23
申请号：US16676023
申请日：2019-11-06
Applicant: SanDisk Technologies LLC
Inventor： Zhiping Zhang , Muhammad Masuduzzaman , Huai-Yuan Tseng , Peng Zhang , Dengtao Zhao , Deepanshu Dutta
Abstract: A method reading memory using bi-directional sensing, including programming first memory cells coupled to a first word-line using a normal programming order; programming second memory cells coupled to a second word-line using a normal programming order; reading data from the first memory cells by applying a normal sensing operation to the first word-line; and reading data from the second memory cells by applying a reverse sensing operation to the second word-line. Methods also include receiving an error associated with reading data from the first memory cells; and then reading the data from the first memory cells by applying a reverse sensing operation to the first word-line. Method also include receiving an error associated with reading the data from the second memory cells; and then reading the data from the second memory cells by applying a normal sensing operation to the second word-line.
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Patent Agency Ranking
公开(公告)号：US12112800B2
公开(公告)日：2024-10-08
申请号：US17825048
申请日：2022-05-26
Applicant: SanDisk Technologies LLC
Inventor： Xiang Yang , Deepanshu Dutta , Muhammad Masuduzzaman , Jiacen Guo
CPC classification number: G11C11/5628 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/24 , G11C16/26
Abstract: A method for programming a memory array of a non-volatile memory structure, wherein the memory array comprises a population of MLC NAND-type memory cells, and the method comprises: (1) in a first program pulse, programming selected memory cells according to a first programmable state and a second programmable state, and (2) in a second program pulse, programming the selected memory cells according to a third programmable state.
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公开(公告)号：US20240071524A1
公开(公告)日：2024-02-29
申请号：US17895412
申请日：2022-08-25
Applicant: SanDisk Technologies LLC
Inventor： Xiang Yang , Henry Chin , Erika Penzo , Muhammad Masuduzzaman
CPC classification number: G11C16/3459 , G11C16/102 , G11C16/14 , G11C16/3404
Abstract: Technology is disclosed herein for smart verify in a memory system that has a four bit per cell program mode (or X4 mode) and also a three bit per cell program mode (or X3 mode). The X3 mode uses a three-bit gray code that is based on a four-bit gray code of the X4 mode. The memory system skips verify of states in the X3 mode, while using a considerable portion of the programming logic from the X4 mode. In one X3 mode the memory system skips B-state verify while the number of memory cells having a Vt above an A-state verify voltage is below a threshold. In one X3 mode the memory system determines whether to skip verify for a first set of data states based on a first test and determines whether to skip verify for a second set of data states based on a second test.
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8.发明申请公开(公告)号：US20220215873A1
公开(公告)日：2022-07-07
申请号：US17142753
申请日：2021-01-06
Applicant: SanDisk Technologies LLC
Inventor： Sujjatul Islam , Muhammad Masuduzzaman , Ravi Kumar
Abstract: A method for programming a non-volatile memory structure with four-page data, wherein the method comprises, in a first stage, selecting four programmable states of a segment of MLC NAND-type memory cells, programming at least a first of the four programmable states with two pages of a four-page data at a first step voltage level, between programming at least two neighboring programmable states of the four programmable states, increasing the first step voltage level to a second step voltage level for a single program pulse and according to a pre-determined magnitude, and programming a latter of the at least two neighboring programmable states at the first step voltage level.
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公开(公告)号：US20210391025A1
公开(公告)日：2021-12-16
申请号：US16899965
申请日：2020-06-12
Applicant: SanDisk Technologies LLC
Inventor： Muhammad Masuduzzaman , Deepanshu Dutta
Abstract: A method comprises determining a verify voltage for a next iteration of a verify operation to be performed on memory cells a first set of memory cells of a selected word line, and determining data states for a second set of memory cells of at least one neighboring word line. The method further comprises determining, based on the data states, a verify voltage configuration that includes bit line voltage biases or sense times, and performing the next iteration of the verify operation on the selected word line by using the verify voltage configuration to iteratively verify whether respective memory cells, of the second set of memory cells, have threshold voltages above the verify voltage, wherein determining the data states, determining the verify voltage configuration, and performing the next iteration are to be repeated until a program stop condition is satisfied.
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公开(公告)号：US20210134369A1
公开(公告)日：2021-05-06
申请号：US16668675
申请日：2019-10-30
Applicant: SanDisk Technologies LLC
Inventor： Zhiping Zhang , Muhammad Masuduzzaman , Huai-Yuan Tseng , Dengtao Zhao , Deepanshu Dutta
IPC: G11C16/10 , G11C16/24 , G11C11/4074 , G11C11/409
Abstract: A method of concurrently programming a memory. Various methods include: applying a non-negative voltage on a first bit line coupled to a first memory cell; applying a negative voltage on a second bit line coupled to a second memory cell, where the negative voltage is generated using triple-well technology; then applying a programming pulse to the first and second memory cells concurrently; and in response, programming the first and second memory cells to different states. The methods also include applying a quick pass write operation to the first and second memory cells, by: applying a quick pass write voltage to the first bit line coupled to the fist memory cell, where the quick pass write voltage is higher than the non-negative voltage; applying a negative quick pass write voltage to the second bit line coupled to the first memory cell, where the negative quick pass write voltage is generated using triple-well technology.
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